Hi: There're many pairs of define_insn/define_expand that are very similar to each other except mode iterator and condition. For these patterns VI12_AVX512VL are used under condition TARGET_AVX512BW, and VI48_AVX512VL are used under condition TARGET_AVX512F.
This patch is about to introduce a new iterator VI_AVX512VLBW to combine a pair of those patterns into one. There are no functional changes, just code refactoring. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? gcc/ChangeLog * config/i386/sse.md (VI_AVX512VLBW): New mode iterator. (<avx512>_ucmp<mode>3<mask_scalar_merge_name>): Combine two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL into one pattern with mode iterator VI_AVX512VLBW. (vec_cmpu<mode><avx512fmaskmodelower>): Ditto. (<avx512>_cvt<ssemodesuffix>2mask<mode>): Ditto. (<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto. (*<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto. (<plusminus_insn><mode>3_mask): Ditto. (*<plusminus_insn><mode>3_mask): Ditto. (<avx512>_eq<mode>3<mask_scalar_merge_name>): Ditto. (<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Ditto. (<avx512>_gt<mode>3<mask_scalar_merge_name>): Ditto. (<sse2_avx2>_andnot<mode>3_mask): Ditto. (abs<mode>2_mask): Ditto. (*<avx512>_<code><mode>3<mask_name>): Combine from ... (*avx512f_<code><mode>3<mask_name>) and (<mask_codefor><code><mode>3<mask_name>). -- BR, Hongtao
From e55528fb9a0346365327e7b1cdebadec7c71be15 Mon Sep 17 00:00:00 2001 From: liuhongt <hongtao....@intel.com> Date: Mon, 30 Nov 2020 13:24:45 +0800 Subject: [PATCH] Combine VI12_AVX512VL with VI48_AVX512VL into VI_AVX512VLBW. There're many pairs of define_insn/define_expand that are very similar to each other except mode iterator and condition. For these patterns VI12_AVX512VL are used under condition TARGET_AVX512BW, and VI48_AVX512VL are used under condition TARGET_AVX512F. This patch is about to introduce a new iterator VI_AVX512VLBW to combine a pair of those patterns into one. There're no functional changed, just code refactoring. gcc/ChangeLog * config/i386/sse.md (VI_AVX512VLBW): New mode iterator. (<avx512>_ucmp<mode>3<mask_scalar_merge_name>): Combine two patterns with mode iterator VI12_AVX512VL and VI48_AVX512VL into one pattern with mode iterator VI_AVX512VLBW. (vec_cmpu<mode><avx512fmaskmodelower>): Ditto. (<avx512>_cvt<ssemodesuffix>2mask<mode>): Ditto. (<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto. (*<avx512>_cvtmask2<ssemodesuffix><mode>): Ditto. (<plusminus_insn><mode>3_mask): Ditto. (*<plusminus_insn><mode>3_mask): Ditto. (<avx512>_eq<mode>3<mask_scalar_merge_name>): Ditto. (<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Ditto. (<avx512>_gt<mode>3<mask_scalar_merge_name>): Ditto. (<sse2_avx2>_andnot<mode>3_mask): Ditto. (abs<mode>2_mask): Ditto. (*<avx512>_<code><mode>3<mask_name>): Combine from ... (*avx512f_<code><mode>3<mask_name>) and (<mask_codefor><code><mode>3<mask_name>). --- gcc/config/i386/sse.md | 312 ++++++++++++----------------------------- 1 file changed, 89 insertions(+), 223 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4aad462f882..c761a018e86 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -335,6 +335,14 @@ (define_mode_iterator VI48_AVX512VL [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) +(define_mode_iterator VI_AVX512VLBW + [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + (V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") + (V16QI "TARGET_AVX512BW && TARGET_AVX512VL") + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW") + (V8HI "TARGET_AVX512VL && TARGET_AVX512BW")]) + (define_mode_iterator VF_AVX512VL [V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) @@ -2981,25 +2989,11 @@ (define_insn "<avx512>_cmp<mode>3<mask_scalar_merge_name>" (define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") (unspec:<avx512fmaskmode> - [(match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm") + [(match_operand:VI_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm") (match_operand:SI 3 "const_0_to_7_operand" "n")] UNSPEC_UNSIGNED_PCMP))] - "TARGET_AVX512BW" - "vpcmpu<ssemodesuffix>\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}" - [(set_attr "type" "ssecmp") - (set_attr "length_immediate" "1") - (set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - -(define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>" - [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") - (unspec:<avx512fmaskmode> - [(match_operand:VI48_AVX512VL 1 "register_operand" "v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_7_operand" "n")] - UNSPEC_UNSIGNED_PCMP))] - "TARGET_AVX512F" + "" "vpcmpu<ssemodesuffix>\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}" [(set_attr "type" "ssecmp") (set_attr "length_immediate" "1") @@ -3149,22 +3143,9 @@ (define_expand "vec_cmp<mode><sseintvecmodelower>" (define_expand "vec_cmpu<mode><avx512fmaskmodelower>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand") (match_operator:<avx512fmaskmode> 1 "" - [(match_operand:VI48_AVX512VL 2 "register_operand") - (match_operand:VI48_AVX512VL 3 "nonimmediate_operand")]))] - "TARGET_AVX512F" -{ - bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]), - operands[2], operands[3]); - gcc_assert (ok); - DONE; -}) - -(define_expand "vec_cmpu<mode><avx512fmaskmodelower>" - [(set (match_operand:<avx512fmaskmode> 0 "register_operand") - (match_operator:<avx512fmaskmode> 1 "" - [(match_operand:VI12_AVX512VL 2 "register_operand") - (match_operand:VI12_AVX512VL 3 "nonimmediate_operand")]))] - "TARGET_AVX512BW" + [(match_operand:VI_AVX512VLBW 2 "register_operand") + (match_operand:VI_AVX512VLBW 3 "nonimmediate_operand")]))] + "" { bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]), operands[2], operands[3]); @@ -6428,71 +6409,53 @@ (define_insn "vec_unpacks_lo_v16sf" (define_insn "<avx512>_cvt<ssemodesuffix>2mask<mode>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") (unspec:<avx512fmaskmode> - [(match_operand:VI12_AVX512VL 1 "register_operand" "v")] - UNSPEC_CVTINT2MASK))] - "TARGET_AVX512BW" - "vpmov<ssemodesuffix>2m\t{%1, %0|%0, %1}" - [(set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - -(define_insn "<avx512>_cvt<ssemodesuffix>2mask<mode>" - [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") - (unspec:<avx512fmaskmode> - [(match_operand:VI48_AVX512VL 1 "register_operand" "v")] + [(match_operand:VI_AVX512VLBW 1 "register_operand" "v")] UNSPEC_CVTINT2MASK))] - "TARGET_AVX512DQ" + "TARGET_AVX512DQ || GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) < 4" "vpmov<ssemodesuffix>2m\t{%1, %0|%0, %1}" [(set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) (define_expand "<avx512>_cvtmask2<ssemodesuffix><mode>" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW (match_dup 2) (match_dup 3) (match_operand:<avx512fmaskmode> 1 "register_operand")))] - "TARGET_AVX512BW" - { - operands[2] = CONSTM1_RTX (<MODE>mode); - operands[3] = CONST0_RTX (<MODE>mode); - }) - -(define_insn "*<avx512>_cvtmask2<ssemodesuffix><mode>" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (match_operand:VI12_AVX512VL 2 "vector_all_ones_operand") - (match_operand:VI12_AVX512VL 3 "const0_operand") - (match_operand:<avx512fmaskmode> 1 "register_operand" "k")))] - "TARGET_AVX512BW" - "vpmovm2<ssemodesuffix>\t{%1, %0|%0, %1}" - [(set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - -(define_expand "<avx512>_cvtmask2<ssemodesuffix><mode>" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (match_dup 2) - (match_dup 3) - (match_operand:<avx512fmaskmode> 1 "register_operand")))] - "TARGET_AVX512F" + "" "{ operands[2] = CONSTM1_RTX (<MODE>mode); operands[3] = CONST0_RTX (<MODE>mode); }") (define_insn "*<avx512>_cvtmask2<ssemodesuffix><mode>" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v,v") - (vec_merge:VI48_AVX512VL - (match_operand:VI48_AVX512VL 2 "vector_all_ones_operand") - (match_operand:VI48_AVX512VL 3 "const0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v,v") + (vec_merge:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 2 "vector_all_ones_operand") + (match_operand:VI_AVX512VLBW 3 "const0_operand") (match_operand:<avx512fmaskmode> 1 "register_operand" "k,Yk")))] - "TARGET_AVX512F" + "" "@ vpmovm2<ssemodesuffix>\t{%1, %0|%0, %1} vpternlog<ssemodesuffix>\t{$0x81, %0, %0, %0%{%1%}%{z%}|%0%{%1%}%{z%}, %0, %0, 0x81}" - [(set_attr "isa" "avx512dq,*") + [(set (attr "isa") + (cond [(eq_attr "alternative" "0") + (if_then_else + (match_test "GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) > 2") + (const_string "avx512dq") + (const_string "*")) + ] + (const_string "*"))) (set_attr "length_immediate" "0,1") (set_attr "prefix" "evex") + (set (attr "enabled") + (cond [(eq_attr "alternative" "1") + (if_then_else + (match_test "GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) < 4") + (symbol_ref "false") + (const_string "*")) + ] + (const_string "*"))) (set_attr "mode" "<sseinsnmode>")]) (define_insn "sse2_cvtps2pd<mask_name>" @@ -11334,25 +11297,14 @@ (define_expand "<plusminus_insn><mode>3" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_expand "<plusminus_insn><mode>3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (plusminus:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW + (plusminus:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand") (match_operand:<avx512fmaskmode> 4 "register_operand")))] - "TARGET_AVX512F" - "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") - -(define_expand "<plusminus_insn><mode>3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL - (plusminus:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand") - (match_operand:<avx512fmaskmode> 4 "register_operand")))] - "TARGET_AVX512BW" + "" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*<plusminus_insn><mode>3" @@ -11371,28 +11323,14 @@ (define_insn "*<plusminus_insn><mode>3" (set_attr "mode" "<sseinsnmode>")]) (define_insn "*<plusminus_insn><mode>3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI48_AVX512VL - (plusminus:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "<comm>v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand" "0C") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v") + (vec_merge:VI_AVX512VLBW + (plusminus:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand" "<comm>v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand" "0C") (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] - "TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - -(define_insn "*<plusminus_insn><mode>3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (plusminus:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "<comm>v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand" "0C") - (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))] - "TARGET_AVX512BW && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "vp<plusminus_mnemonic><ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix" "evex") @@ -12309,37 +12247,25 @@ (define_insn "*avx2_<code><mode>3" (set_attr "mode" "OI")]) (define_expand "<code><mode>3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (maxmin:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW + (maxmin:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand") (match_operand:<avx512fmaskmode> 4 "register_operand")))] - "TARGET_AVX512F" + "" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") -(define_insn "*avx512f_<code><mode>3<mask_name>" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") - (maxmin:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_evex") - (set_attr "mode" "<sseinsnmode>")]) - -(define_insn "<mask_codefor><code><mode>3<mask_name>" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (maxmin:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")))] - "TARGET_AVX512BW" +(define_insn "*<avx512>_<code><mode>3<mask_name>" + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v") + (maxmin:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand" "%v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm")))] + "!(MEM_P (operands[1]) && MEM_P (operands[2]))" "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" [(set_attr "type" "sseiadd") - (set_attr "prefix" "evex") + (set_attr "prefix" "<mask_prefix2>") (set_attr "mode" "<sseinsnmode>")]) (define_expand "<code><mode>3" @@ -12572,41 +12498,17 @@ (define_insn "*avx2_eq<mode>3" (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand") (unspec:<avx512fmaskmode> - [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")] + [(match_operand:VI_AVX512VLBW 1 "nonimmediate_operand") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")] UNSPEC_MASKED_EQ))] - "TARGET_AVX512BW" - "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") - -(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>" - [(set (match_operand:<avx512fmaskmode> 0 "register_operand") - (unspec:<avx512fmaskmode> - [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")] - UNSPEC_MASKED_EQ))] - "TARGET_AVX512F" + "" "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k,k") (unspec:<avx512fmaskmode> - [(match_operand:VI12_AVX512VL 1 "nonimm_or_0_operand" "%v,v") - (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "vm,C")] - UNSPEC_MASKED_EQ))] - "TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "@ - vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2} - vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - -(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1" - [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k,k") - (unspec:<avx512fmaskmode> - [(match_operand:VI48_AVX512VL 1 "nonimm_or_0_operand" "%v,v") - (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "vm,C")] + [(match_operand:VI_AVX512VLBW 1 "nonimm_or_0_operand" "%v,v") + (match_operand:VI_AVX512VLBW 2 "nonimm_or_0_operand" "vm,C")] UNSPEC_MASKED_EQ))] "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ @@ -12696,21 +12598,9 @@ (define_insn "avx2_gt<mode>3" (define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>" [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") (unspec:<avx512fmaskmode> - [(match_operand:VI48_AVX512VL 1 "register_operand" "v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))] - "TARGET_AVX512F" - "vpcmpgt<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" - [(set_attr "type" "ssecmp") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - -(define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>" - [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k") - (unspec:<avx512fmaskmode> - [(match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))] - "TARGET_AVX512BW" + [(match_operand:VI_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))] + "" "vpcmpgt<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}" [(set_attr "type" "ssecmp") (set_attr "prefix_extra" "1") @@ -12950,26 +12840,15 @@ (define_expand "<sse2_avx2>_andnot<mode>3" "TARGET_SSE2") (define_expand "<sse2_avx2>_andnot<mode>3_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand") - (vec_merge:VI48_AVX512VL - (and:VI48_AVX512VL - (not:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "register_operand")) - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") - (match_operand:<avx512fmaskmode> 4 "register_operand")))] - "TARGET_AVX512F") - -(define_expand "<sse2_avx2>_andnot<mode>3_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand") - (vec_merge:VI12_AVX512VL - (and:VI12_AVX512VL - (not:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "register_operand")) - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) - (match_operand:VI12_AVX512VL 3 "nonimm_or_0_operand") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand") + (vec_merge:VI_AVX512VLBW + (and:VI_AVX512VLBW + (not:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "register_operand")) + (match_operand:VI_AVX512VLBW 2 "nonimmediate_operand")) + (match_operand:VI_AVX512VLBW 3 "nonimm_or_0_operand") (match_operand:<avx512fmaskmode> 4 "register_operand")))] - "TARGET_AVX512BW") + "") (define_insn "*andnot<mode>3" [(set (match_operand:VI 0 "register_operand" "=x,x,v") @@ -16874,11 +16753,11 @@ (define_insn "*abs<mode>2" (set_attr "mode" "<sseinsnmode>")]) (define_insn "abs<mode>2_mask" - [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI48_AVX512VL - (abs:VI48_AVX512VL - (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm")) - (match_operand:VI48_AVX512VL 2 "nonimm_or_0_operand" "0C") + [(set (match_operand:VI_AVX512VLBW 0 "register_operand" "=v") + (vec_merge:VI_AVX512VLBW + (abs:VI_AVX512VLBW + (match_operand:VI_AVX512VLBW 1 "nonimmediate_operand" "vm")) + (match_operand:VI_AVX512VLBW 2 "nonimm_or_0_operand" "0C") (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))] "TARGET_AVX512F" "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" @@ -16886,19 +16765,6 @@ (define_insn "abs<mode>2_mask" (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) -(define_insn "abs<mode>2_mask" - [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") - (vec_merge:VI12_AVX512VL - (abs:VI12_AVX512VL - (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm")) - (match_operand:VI12_AVX512VL 2 "nonimm_or_0_operand" "0C") - (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))] - "TARGET_AVX512BW" - "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" - [(set_attr "type" "sselog1") - (set_attr "prefix" "evex") - (set_attr "mode" "<sseinsnmode>")]) - (define_expand "abs<mode>2" [(set (match_operand:VI_AVX2 0 "register_operand") (abs:VI_AVX2 -- 2.18.1