This patch enables MVE vorrq instructions for auto-vectorization. MVE
vorrq insns in mve.md are modified to use ior instead of unspec
expression to support ior<mode>3. The ior<mode>3 expander is added to
vec-common.md
2020-12-03 Christophe Lyon <christophe.l...@linaro.org>
gcc/
* config/arm/iterators.md (supf): Remove VORRQ_S and VORRQ_U.
(VORRQ): Remove.
* config/arm/mve.md (mve_vorrq_s<mode>): New entry for vorr
instruction using expression ior.
(mve_vorrq_u<mode>): New expander.
(mve_vorrq_f<mode>): Use ior code instead of unspec.
* config/arm/neon.md (ior<mode>3): Renamed into ior<mode>3_neon.
* config/arm/predicates.md (imm_for_neon_logic_operand): Enable
for MVE.
* config/arm/unspecs.md (VORRQ_S, VORRQ_U, VORRQ_F): Remove.
* config/arm/vec-common.md (ior<mode>3): New expander.
gcc/testsuite/
* gcc.target/arm/simd/mve-vorr.c: Add vorr tests.
---
gcc/config/arm/iterators.md | 5 +--
gcc/config/arm/mve.md | 36 ++++++++++++----
gcc/config/arm/neon.md | 2 +-
gcc/config/arm/predicates.md | 2 +-
gcc/config/arm/unspecs.md | 3 --
gcc/config/arm/vec-common.md | 8 ++++
gcc/testsuite/gcc.target/arm/simd/mve-vorr.c | 64 ++++++++++++++++++++++++++++
7 files changed, 103 insertions(+), 17 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vorr.c
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index badad2b..f0e1d60 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1252,8 +1252,8 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s")
(VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u")
(VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s")
- (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s")
- (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u")
+ (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u")
+ (VQADDQ_N_S "s") (VQADDQ_N_U "u")
(VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s")
(VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u")
(VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s")
@@ -1528,7 +1528,6 @@ (define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U
VMULLTQ_INT_S])
(define_int_iterator VMULQ [VMULQ_U VMULQ_S])
(define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S])
(define_int_iterator VORNQ [VORNQ_U VORNQ_S])
-(define_int_iterator VORRQ [VORRQ_S VORRQ_U])
(define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S])
(define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U])
(define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 238c828..0fcbe62 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1619,17 +1619,36 @@ (define_insn "mve_vornq_<supf><mode>"
;;
;; [vorrq_s, vorrq_u])
;;
-(define_insn "mve_vorrq_<supf><mode>"
+;; signed and unsigned versions are the same: define the unsigned
+;; insn, and use an expander for the signed one as we still reference
+;; both names from arm_mve.h.
+;; We use the same code as in neon.md (TODO: avoid this duplication).
+(define_insn "mve_vorrq_s<mode>"
[
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VORRQ))
+ (set (match_operand:MVE_2 0 "s_register_operand" "=w,w")
+ (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0")
+ (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl")))
]
"TARGET_HAVE_MVE"
- "vorr %q0, %q1, %q2"
+ {
+ switch (which_alternative)
+ {
+ case 0: return "vorr\t%q0, %q1, %q2";
+ case 1: return neon_output_logic_immediate ("vorr", &operands[2],
+ <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));
+ default: gcc_unreachable ();
+ }
+ }
[(set_attr "type" "mve_move")
])
+(define_expand "mve_vorrq_u<mode>"
+ [
+ (set (match_operand:MVE_2 0 "s_register_operand")
+ (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand")
+ (match_operand:MVE_2 2 "neon_logic_op2")))
+ ]
+ "TARGET_HAVE_MVE"
+)
;;
;; [vqaddq_n_s, vqaddq_n_u])
@@ -2664,9 +2683,8 @@ (define_insn "mve_vornq_f<mode>"
(define_insn "mve_vorrq_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
- (match_operand:MVE_0 2 "s_register_operand" "w")]
- VORRQ_F))
+ (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")
+ (match_operand:MVE_0 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
"vorr %q0, %q1, %q2"
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index dc4707d..669c34d 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -690,7 +690,7 @@ (define_insn
"neon_vcvt<NEON_VCVT:nvrint_variant><su_optab><VCVTF:mode><v_cmp_re
(set_attr "predicable" "no")]
)
-(define_insn "ior<mode>3"
+(define_insn "ior<mode>3_neon"
[(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
(match_operand:VDQ 2 "neon_logic_op2" "w,Dl")))]
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 5f58f7c..9f863e1 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -118,7 +118,7 @@ (define_predicate "neon_inv_logic_op2"
(define_predicate "imm_for_neon_logic_operand"
(match_code "const_vector")
{
- return (TARGET_NEON
+ return ((TARGET_NEON || TARGET_HAVE_MVE)
&& neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
})
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 18b3048..c2076c9 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -624,7 +624,6 @@ (define_c_enum "unspec" [
VMULQ_S
VMULQ_N_S
VORNQ_S
- VORRQ_S
VQADDQ_S
VQADDQ_N_S
VQRSHLQ_S
@@ -670,7 +669,6 @@ (define_c_enum "unspec" [
VMULQ_U
VMULQ_N_U
VORNQ_U
- VORRQ_U
VQADDQ_U
VQADDQ_N_U
VQRSHLQ_U
@@ -750,7 +748,6 @@ (define_c_enum "unspec" [
VMULQ_F
VMULQ_N_F
VORNQ_F
- VORRQ_F
VSUBQ_F
VADDLVAQ_U
VADDLVAQ_S
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 2117e5b..df0a6cd 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -180,3 +180,11 @@ (define_expand "and<mode>3"
"TARGET_NEON
|| TARGET_HAVE_MVE"
)
+
+(define_expand "ior<mode>3"
+ [(set (match_operand:VDQ 0 "s_register_operand" "")
+ (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+ (match_operand:VDQ 2 "neon_logic_op2" "")))]
+ "TARGET_NEON
+ || TARGET_HAVE_MVE"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vorr.c
b/gcc/testsuite/gcc.target/arm/simd/mve-vorr.c
new file mode 100644
index 0000000..b1190f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vorr.c
@@ -0,0 +1,64 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \
+ void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
__restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \
+ int i; \
+ for (i=0; i<NB; i++) { \
+ dest[i] = a[i] OP b[i]; \
+ } \
+}
+
+#define FUNC_IMM(SIGN, TYPE, BITS, NB, OP, NAME)
\
+ void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *
__restrict__ dest, TYPE##BITS##_t *a) { \
+ int i; \
+ for (i=0; i<NB; i++) { \
+ dest[i] = a[i] OP 1; \
+ } \
+}
+
+/* 64-bit vectors. */
+FUNC(s, int, 32, 2, |, vorr)
+FUNC(u, uint, 32, 2, |, vorr)
+FUNC(s, int, 16, 4, |, vorr)
+FUNC(u, uint, 16, 4, |, vorr)
+FUNC(s, int, 8, 8, |, vorr)
+FUNC(u, uint, 8, 8, |, vorr)
+
+/* 128-bit vectors. */
+FUNC(s, int, 32, 4, |, vorr)
+FUNC(u, uint, 32, 4, |, vorr)
+FUNC(s, int, 16, 8, |, vorr)
+FUNC(u, uint, 16, 8, |, vorr)
+FUNC(s, int, 8, 16, |, vorr)
+FUNC(u, uint, 8, 16, |, vorr)
+
+/* 64-bit vectors. */
+FUNC_IMM(s, int, 32, 2, |, vorrimm)
+FUNC_IMM(u, uint, 32, 2, |, vorrimm)
+FUNC_IMM(s, int, 16, 4, |, vorrimm)
+FUNC_IMM(u, uint, 16, 4, |, vorrimm)
+FUNC_IMM(s, int, 8, 8, |, vorrimm)
+FUNC_IMM(u, uint, 8, 8, |, vorrimm)
+
+/* 128-bit vectors. */
+FUNC_IMM(s, int, 32, 4, |, vorrimm)
+FUNC_IMM(u, uint, 32, 4, |, vorrimm)
+FUNC_IMM(s, int, 16, 8, |, vorrimm)
+FUNC_IMM(u, uint, 16, 8, |, vorrimm)
+FUNC_IMM(s, int, 8, 16, |, vorrimm)
+FUNC_IMM(u, uint, 8, 16, |, vorrimm)
+
+/* MVE has only 128-bit vectors, so we can vectorize only half of the
+ functions above. */
+/* Although float16 and float32 types are supported at assembly level,
+ we cannot test them with the '|' operator, so we check only the
+ integer variants. */
+/* We emit vorr.i[16|32] qX, #1 for the first four versions of the
+ 128-bit vector vorrimm tests. */
+/* { dg-final { scan-assembler-times {vorr\tq[0-9]+, q[0-9]+, q[0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {vorr.i[0-9]+\tq[0-9]+} 4 } } */
--
2.7.4
