Update size attribute for Power10.
This patch was broken out from my larger patch to update various attributes for
Power10, in order to make the review process hopefully easier. This patch only
updates the size attribute for various new instructions. There were no changes
requested to this portion of the original patch, so nothing is new here.
Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok
for trunk?
-Pat
2020-11-08 Pat Haugen <pthau...@linux.ibm.com>
gcc/
* config/rs6000/dfp.md (extendddtd2, trunctddd2, *cmp<mode>_internal1,
floatditd2, ftrunc<mode>2, fix<mode>di2, dfp_ddedpd_<mode>,
dfp_denbcd_<mode>, dfp_dxex_<mode>, dfp_diex_<mode>,
*dfp_sgnfcnc_<mode>, dfp_dscli_<mode>, dfp_dscri_<mode>): Update size
attribute for Power10.
* config/rs6000/mma.md (*movoo): Likewise.
* config/rs6000/rs6000.md (define_attr "size"): Add 256.
(define_mode_attr bits): Add DD/TD modes.
* config/rs6000/sync.md (load_quadpti, store_quadpti, load_lockedpti,
store_conditionalpti): Update size attribute for Power10.
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 9a952300cd6..7562e63a919 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -139,7 +139,8 @@ (define_insn "extendddtd2"
(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctqpq %0,%1"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "128")])
;; The result of drdpq is an even/odd register pair with the converted
;; value in the even register and zero in the odd register.
@@ -153,6 +154,7 @@ (define_insn "trunctddd2"
"TARGET_DFP"
"drdpq %2,%1\;fmr %0,%2"
[(set_attr "type" "dfp")
+ (set_attr "size" "128")
(set_attr "length" "8")])
(define_insn "trunctdsd2"
@@ -206,7 +208,8 @@ (define_insn "*cmp<mode>_internal1"
(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcmpu<q> %0,%1,%2"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
(define_insn "floatdidd2"
[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
@@ -220,7 +223,8 @@ (define_insn "floatditd2"
(float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dcffixq %0,%1"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "128")])
;; Convert a decimal64/128 to a decimal64/128 whose value is an integer.
;; This is the first stage of converting it to an integer type.
@@ -230,7 +234,8 @@ (define_insn "ftrunc<mode>2"
(fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"drintn<q>. 0,%0,%1,1"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
;; Convert a decimal64/128 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.
@@ -240,7 +245,8 @@ (define_insn "fix<mode>di2"
(fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
"TARGET_DFP"
"dctfix<q> %0,%1"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
;; Decimal builtin support
@@ -262,7 +268,8 @@ (define_insn "dfp_ddedpd_<mode>"
UNSPEC_DDEDPD))]
"TARGET_DFP"
"ddedpd<q> %1,%0,%2"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
(define_insn "dfp_denbcd_<mode>"
[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
@@ -271,7 +278,8 @@ (define_insn "dfp_denbcd_<mode>"
UNSPEC_DENBCD))]
"TARGET_DFP"
"denbcd<q> %1,%0,%2"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
(define_insn "dfp_denbcd_v16qi_inst"
[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
@@ -301,7 +309,8 @@ (define_insn "dfp_dxex_<mode>"
UNSPEC_DXEX))]
"TARGET_DFP"
"dxex<q> %0,%1"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
(define_insn "dfp_diex_<mode>"
[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
@@ -310,7 +319,8 @@ (define_insn "dfp_diex_<mode>"
UNSPEC_DXEX))]
"TARGET_DFP"
"diex<q> %0,%1,%2"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
(define_expand "dfptstsfi_<code>_<mode>"
[(set (match_dup 3)
@@ -349,7 +359,8 @@ (define_insn "*dfp_sgnfcnc_<mode>"
operands[1] = GEN_INT (63);
return "dtstsfi<q> %0,%1,%2";
}
- [(set_attr "type" "fp")])
+ [(set_attr "type" "fp")
+ (set_attr "size" "<bits>")])
(define_insn "dfp_dscli_<mode>"
[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
@@ -358,7 +369,8 @@ (define_insn "dfp_dscli_<mode>"
UNSPEC_DSCLI))]
"TARGET_DFP"
"dscli<q> %0,%1,%2"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
(define_insn "dfp_dscri_<mode>"
[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
@@ -367,4 +379,5 @@ (define_insn "dfp_dscri_<mode>"
UNSPEC_DSCRI))]
"TARGET_DFP"
"dscri<q> %0,%1,%2"
- [(set_attr "type" "dfp")])
+ [(set_attr "type" "dfp")
+ (set_attr "size" "<bits>")])
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 4d291c42f7a..5768a8998e2 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -288,6 +288,7 @@ (define_insn_and_split "*movoo"
DONE;
}
[(set_attr "type" "vecload,vecstore,veclogical")
+ (set_attr "size" "256,256,*")
(set_attr "length" "*,*,8")])
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b89990f46bf..9bd55e7e107 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -209,7 +209,7 @@ (define_attr "type"
;; What data size does this instruction work on?
;; This is used for insert, mul and others as necessary.
-(define_attr "size" "8,16,32,64,128" (const_string "32"))
+(define_attr "size" "8,16,32,64,128,256" (const_string "32"))
;; What is the insn_cost for this insn? The target hook can still override
;; this. For optimizing for size the "length" attribute is used instead.
@@ -670,7 +670,8 @@ (define_mode_attr du_or_d [(QI "du")
;; How many bits in this mode?
(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")
- (SF "32") (DF "64")])
+ (SF "32") (DF "64")
+ (DD "64") (TD "128")])
; DImode bits
(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md
index 5ad88806818..b07b2e86aae 100644
--- a/gcc/config/rs6000/sync.md
+++ b/gcc/config/rs6000/sync.md
@@ -131,6 +131,7 @@ (define_insn "load_quadpti"
&& !reg_mentioned_p (operands[0], operands[1])"
"lq %0,%1"
[(set_attr "type" "load")
+ (set_attr "size" "128")
(set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED")
(const_string "yes")
(const_string "no")))])
@@ -205,6 +206,7 @@ (define_insn "store_quadpti"
"TARGET_SYNC_TI"
"stq %1,%0"
[(set_attr "type" "store")
+ (set_attr "size" "128")
(set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED")
(const_string "yes")
(const_string "no")))])
@@ -333,7 +335,8 @@ (define_insn "load_lockedpti"
&& !reg_mentioned_p (operands[0], operands[1])
&& quad_int_reg_operand (operands[0], PTImode)"
"lqarx %0,%y1"
- [(set_attr "type" "load_l")])
+ [(set_attr "type" "load_l")
+ (set_attr "size" "128")])
(define_insn "store_conditional<mode>"
[(set (match_operand:CC 0 "cc_reg_operand" "=x")
@@ -394,7 +397,8 @@ (define_insn "store_conditionalpti"
(match_operand:PTI 2 "quad_int_reg_operand" "r"))]
"TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"
"stqcx. %2,%y1"
- [(set_attr "type" "store_c")])
+ [(set_attr "type" "store_c")
+ (set_attr "size" "128")])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "int_reg_operand") ;; bool out
