Update prefixed attribute for Power10.
This patch was broken out from my larger patch to update various attributes for
Power10, in order to make the review process hopefully easier. This patch only
updates the prefix attribute for various new instructions. Changes in this
version include missed updates to rs6000_insn_cost and
rs6000_adjust_insn_length. I stayed with the new 'always' keyword but added
additional commentary so hopefully is more clear.
Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok
for trunk?
-Pat
2020-11-10 Pat Haugen <pthau...@linux.ibm.com>
gcc/
* config/rs6000/altivec.md (xxspltiw_v4si, xxspltiw_v4sf_inst,
xxspltidp_v2df_inst, xxsplti32dx_v4si_inst, xxsplti32dx_v4sf_inst,
xxblend_<mode>, xxpermx_inst, xxeval): Mark prefixed "always".
* config/rs6000/mma.md (mma_<vvi4i4i8>, mma_<avvi4i4i8>,
mma_<vvi4i4i2>, mma_<avvi4i4i2>, mma_<vvi4i4>, mma_<avvi4i4>,
mma_<pvi4i2>, mma_<apvi4i2>, mma_<vvi4i4i4>, mma_<avvi4i4i4>):
Likewise.
* config/rs6000/rs6000.c (rs6000_insn_cost): Update test for prefixed
insn.
(next_insn_prefixed_p): Rename to prefix_next_insn_p.
(rs6000_final_prescan_insn): Only add 'p' for PREFIXED_YES.
(rs6000_asm_output_opcode): Adjust.
(rs6000_adjust_insn_length): Update test for prefixed insns.
* config/rs6000/rs6000.md (define_attr "prefixed"): Add 'always'
and update commentary.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 6a6ce0f84ed..fc926f7a7aa 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -828,7 +828,8 @@ (define_insn "xxspltiw_v4si"
UNSPEC_XXSPLTIW))]
"TARGET_POWER10"
"xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_expand "xxspltiw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=wa")
@@ -847,7 +848,8 @@ (define_insn "xxspltiw_v4sf_inst"
UNSPEC_XXSPLTIW))]
"TARGET_POWER10"
"xxspltiw %x0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_expand "xxspltidp_v2df"
[(set (match_operand:V2DF 0 "register_operand" )
@@ -866,7 +868,8 @@ (define_insn "xxspltidp_v2df_inst"
UNSPEC_XXSPLTID))]
"TARGET_POWER10"
"xxspltidp %x0,%1"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
@@ -895,7 +898,8 @@ (define_insn "xxsplti32dx_v4si_inst"
UNSPEC_XXSPLTI32DX))]
"TARGET_POWER10"
"xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_expand "xxsplti32dx_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=wa")
@@ -923,7 +927,8 @@ (define_insn "xxsplti32dx_v4sf_inst"
UNSPEC_XXSPLTI32DX))]
"TARGET_POWER10"
"xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_insn "xxblend_<mode>"
[(set (match_operand:VM3 0 "register_operand" "=wa")
@@ -933,7 +938,8 @@ (define_insn "xxblend_<mode>"
UNSPEC_XXBLEND))]
"TARGET_POWER10"
"xxblendv<VM3_char> %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_expand "xxpermx"
[(set (match_operand:V2DI 0 "register_operand" "+wa")
@@ -977,7 +983,8 @@ (define_insn "xxpermx_inst"
UNSPEC_XXPERMX))]
"TARGET_POWER10"
"xxpermx %x0,%x1,%x2,%x3,%4"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_expand "vstrir_<mode>"
[(set (match_operand:VIshort 0 "altivec_register_operand")
@@ -3625,7 +3632,8 @@ (define_insn "xxeval"
UNSPEC_XXEVAL))]
"TARGET_POWER10"
"xxeval %0,%1,%2,%3,%4"
- [(set_attr "type" "vecsimple")])
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "always")])
(define_expand "vec_unpacku_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 4d291c42f7a..a87a1eb132c 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -540,6 +540,7 @@ (define_insn "mma_<vvi4i4i8>"
"TARGET_MMA"
"<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<avvi4i4i8>"
@@ -554,6 +555,7 @@ (define_insn "mma_<avvi4i4i8>"
"TARGET_MMA"
"<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<vvi4i4i2>"
@@ -567,6 +569,7 @@ (define_insn "mma_<vvi4i4i2>"
"TARGET_MMA"
"<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<avvi4i4i2>"
@@ -581,6 +584,7 @@ (define_insn "mma_<avvi4i4i2>"
"TARGET_MMA"
"<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<vvi4i4>"
@@ -593,6 +597,7 @@ (define_insn "mma_<vvi4i4>"
"TARGET_MMA"
"<vvi4i4> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<avvi4i4>"
@@ -606,6 +611,7 @@ (define_insn "mma_<avvi4i4>"
"TARGET_MMA"
"<avvi4i4> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<pvi4i2>"
@@ -618,6 +624,7 @@ (define_insn "mma_<pvi4i2>"
"TARGET_MMA"
"<pvi4i2> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<apvi4i2>"
@@ -631,6 +638,7 @@ (define_insn "mma_<apvi4i2>"
"TARGET_MMA"
"<apvi4i2> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<vvi4i4i4>"
@@ -644,6 +652,7 @@ (define_insn "mma_<vvi4i4i4>"
"TARGET_MMA"
"<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
(define_insn "mma_<avvi4i4i4>"
@@ -658,4 +667,5 @@ (define_insn "mma_<avvi4i4i4>"
"TARGET_MMA"
"<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
+ (set_attr "prefixed" "always")
(set_attr "length" "8")])
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f26fc13484b..c7b877d41cd 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -21852,7 +21852,7 @@ rs6000_insn_cost (rtx_insn *insn, bool speed)
if (n == 0)
{
int length = get_attr_length (insn);
- if (get_attr_prefixed (insn) == PREFIXED_YES)
+ if (get_attr_prefixed (insn) != PREFIXED_NO)
{
int adjust = 0;
ADJUST_INSN_LENGTH (insn, adjust);
@@ -25971,7 +25971,7 @@ prefixed_paddi_p (rtx_insn *insn)
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
-static bool next_insn_prefixed_p;
+static bool prefix_next_insn_p;
/* Define FINAL_PRESCAN_INSN if some processing needs to be done before
outputting the assembler code. On the PowerPC, we remember if the current
@@ -25982,7 +25982,8 @@ static bool next_insn_prefixed_p;
void
rs6000_final_prescan_insn (rtx_insn *insn, rtx [], int)
{
- next_insn_prefixed_p = (get_attr_prefixed (insn) != PREFIXED_NO);
+ /* Only PREFIXED_YES insns need a 'p' emitted before the opcode. */
+ prefix_next_insn_p = (get_attr_prefixed (insn) == PREFIXED_YES);
return;
}
@@ -25992,7 +25993,7 @@ rs6000_final_prescan_insn (rtx_insn *insn, rtx [], int)
void
rs6000_asm_output_opcode (FILE *stream)
{
- if (next_insn_prefixed_p)
+ if (prefix_next_insn_p)
fprintf (stream, "p");
return;
@@ -26019,7 +26020,7 @@ rs6000_adjust_insn_length (rtx_insn *insn, int length)
{
rtx pattern = PATTERN (insn);
if (GET_CODE (pattern) != USE && GET_CODE (pattern) != CLOBBER
- && get_attr_prefixed (insn) == PREFIXED_YES)
+ && get_attr_prefixed (insn) != PREFIXED_NO)
{
int num_prefixed = get_attr_max_prefixed_insns (insn);
length += 4 * (num_prefixed + 1);
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b89990f46bf..44759bfc6ce 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -264,13 +264,17 @@ (define_attr "var_shift" "no,yes"
(define_attr "cannot_copy" "no,yes" (const_string "no"))
-;; Whether an insn is a prefixed insn, and an initial 'p' should be printed
-;; before the instruction. A prefixed instruction has a prefix instruction
-;; word that extends the immediate value of the instructions from 12-16 bits to
-;; 34 bits. The macro ASM_OUTPUT_OPCODE emits a leading 'p' for prefixed
-;; insns. The default "length" attribute will also be adjusted by default to
-;; be 12 bytes.
-(define_attr "prefixed" "no,yes"
+;; Whether an insn is a prefixed insn. A prefixed instruction has a prefix
+;; instruction word that conveys additional information such as a larger
+;; immediate, additional operands, etc., in addition to the normal instruction
+;; word. The values and there meaning are:
+;; PREFIXED_NO - insn is not prefixed
+;; PREFIXED_YES - insn is prefixed and requires a 'p' before the opcode
+;; PREFIXED_ALWAYS - insn is prefixed but does not require a 'p'
+;; The macro ASM_OUTPUT_OPCODE emits a leading 'p' for prefixed="yes" insns.
+;; The default "length" attribute will also be adjusted by default to be 12
+;; bytes.
+(define_attr "prefixed" "no,yes,always"
(cond [(ior (match_test "!TARGET_PREFIXED")
(match_test "!NONJUMP_INSN_P (insn)"))
(const_string "no")
