On Mon, Apr 12, 2021 at 3:20 PM Uros Bizjak via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> On Mon, Apr 12, 2021 at 5:13 AM Cui, Lili <lili....@intel.com> wrote:
> >
> > Hi Uros,
> >
> > This patch is about to change Alder Lake ISA list to GCC add m_ALDERLAKE to
> > m_CORE_AVX2.
> > Alder Lake Intel Hybrid Technology is based on Tremont and plus
> > ADCX/AVX/AVX2/BMI/BMI2/F16C/FMA/LZCNT/
> > PCONFIG/PKU/VAES/VPCLMULQDQ/SERIALIZE/HRESET/KL/WIDEKL/AVX-VNNI
> > For detailed information, please refer to
> > https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
> >
> > Bootstrap is ok, and no regressions for i386/x86-64 testsuite.
> >
> > OK for master backport to GCC 10?
This should be a typo, no need to backport since -march=alderlake is
introduced in GCC11.
I've committed the patch, thx for the review.
>
> OK for both.
>
> Thanks,
> Uros.
>
> > [PATCH] Change march=alderlake ISA list and add m_ALDERLAKE to
> > m_CORE_AVX2
> >
> > Alder Lake Intel Hybrid Technology will not support Intel(r) AVX-512. ISA
> > features such as Intel(r) AVX, AVX-VNNI, Intel(r) AVX2, and
> > UMONITOR/UMWAIT/TPAUSE
> > are supported.
> >
> > gcc/
> > * config/i386/i386.h
> > (PTA_ALDERLAKE): Change alderlake ISA list.
> > * config/i386/i386-options.c
> > (m_CORE_AVX2): Add m_ALDERLAKE.
> > *common/config/i386/cpuinfo.h:
> > (get_intel_cpu): Add rocketlake model.
> > * doc/invoke.texi: Change alderlake ISA list.
> > ---
> > gcc/common/config/i386/cpuinfo.h | 1 +
> > gcc/config/i386/i386-options.c | 2 +-
> > gcc/config/i386/i386.h | 7 ++++---
> > gcc/doc/invoke.texi | 9 +++++----
> > 4 files changed, 11 insertions(+), 8 deletions(-)
> >
> > diff --git a/gcc/common/config/i386/cpuinfo.h
> > b/gcc/common/config/i386/cpuinfo.h
> > index dbce022620a..c1ee7a1f8b8 100644
> > --- a/gcc/common/config/i386/cpuinfo.h
> > +++ b/gcc/common/config/i386/cpuinfo.h
> > @@ -476,6 +476,7 @@ get_intel_cpu (struct __processor_model *cpu_model,
> > cpu_model->__cpu_subtype = INTEL_COREI7_TIGERLAKE;
> > break;
> > case 0x97:
> > + case 0x9a: /* Alder Lake. */
> > cpu = "alderlake";
> > CHECK___builtin_cpu_is ("corei7");
> > diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c
> > index a8d06735d79..02e9c97d174 100644
> > --- a/gcc/config/i386/i386-options.c
> > +++ b/gcc/config/i386/i386-options.c
> > @@ -129,7 +129,7 @@ along with GCC; see the file COPYING3. If not see
> > #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
> > | m_ICELAKE_CLIENT | m_ICELAKE_SERVER |
> > m_CASCADELAKE \
> > | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS)
> > -#define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
> > +#define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_ALDERLAKE | m_CORE_AVX512)
> > #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2)
> > #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
> > #define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS)
> > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> > index b4001d21b70..24894b4422a 100644
> > --- a/gcc/config/i386/i386.h
> > +++ b/gcc/config/i386/i386.h
> > @@ -2547,9 +2547,6 @@ constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS =
> > PTA_COOPERLAKE | PTA_MOVDIRI
> > | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_ENQCMD | PTA_CLDEMOTE
> > | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE
> > | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI;
> > -constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE
> > - | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_HRESET | PTA_KL
> > - | PTA_WIDEKL | PTA_AVXVNNI;
> > constexpr wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF
> > | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
> > constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
> > @@ -2562,6 +2559,10 @@ constexpr wide_int_bitmask PTA_GOLDMONT_PLUS =
> > PTA_GOLDMONT | PTA_RDPID
> > | PTA_SGX | PTA_PTWRITE;
> > constexpr wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
> > | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG;
> > +constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX
> > + | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT
> > + | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE
> > + | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
> > constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
> > | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
> >
> > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> > index 46876ea2961..6b585cec740 100644
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -30188,10 +30188,11 @@ instruction set support.
> >
> > @item alderlake
> > Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> > SSSE3,
> > -SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI,
> > -BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, CLDEMOTE,
> > -PTWRITE, WAITPKG, SERIALIZE, KEYLOCKER, HRESET and AVX-VNNI instruction set
> > -support.
> > +SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
> > XSAVES,
> > +XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, MOVDIRI,
> > +MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
> > +PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL and AVX-VNNI
> > +instruction set support.
> > @item k6
> > AMD K6 CPU with MMX instruction set support.
> > --
> > 2.17.1
> >
> > Thanks,
> > Lili.
> >
> >
--
BR,
Hongtao
