On Sat, Apr 10, 2021 at 5:11 PM H.J. Lu via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Add inline_ignore_target function attribute to inform the compiler that
> target specific option mismatch on functions with the always_inline
> attribute may be ignored. On x86 targets, this attribute can be used on
> integer functions to ignore target non-integer option mismatch.
I'm not sure I like such attribute but please adjust default_target_can_inline_p
accordingly (only few targets override this hook).
Richard.
> gcc/c-family/
>
> PR target/99744
> * c-family/c-attribs.c (c_common_attribute_table): Add
> inline_ignore_target.
>
> gcc/
>
> PR target/99744
> * common/config/i386/i386-common.c (OPTION_MASK_*) to ...
> * common/config/i386/i386-common.h: Here. New file.
> * config/i386/i386.c (ix86_can_inline_p): Ignore target
> non-integer option mismatch if callee has inline_ignore_target
> attribute.
> * config/i386/i386.h: Include common/config/i386/i386-common.h.
> * config/i386/ia32intrin.h (__rdtsc): Use always_inline function
> with inline_ignore_target attribute.
> (__rdtscp): Likewise.
> * config/i386/serializeintrin.h (_serialize): Likewise.
> * doc/extend.texi: Document inline_ignore_target function
> attribute.
>
> gcc/testsuite/
>
> PR target/99744
> * gcc.target/i386/pr99744-3.c: New test.
> ---
> gcc/c-family/c-attribs.c | 2 +
> gcc/common/config/i386/i386-common.c | 297 --------------------
> gcc/common/config/i386/i386-common.h | 315 ++++++++++++++++++++++
> gcc/config/i386/i386.c | 41 ++-
> gcc/config/i386/i386.h | 1 +
> gcc/config/i386/ia32intrin.h | 16 +-
> gcc/config/i386/serializeintrin.h | 8 +-
> gcc/doc/extend.texi | 8 +
> gcc/testsuite/gcc.target/i386/pr99744-3.c | 13 +
> 9 files changed, 396 insertions(+), 305 deletions(-)
> create mode 100644 gcc/common/config/i386/i386-common.h
> create mode 100644 gcc/testsuite/gcc.target/i386/pr99744-3.c
>
> diff --git a/gcc/c-family/c-attribs.c b/gcc/c-family/c-attribs.c
> index c1f652d1dc9..863936af7ca 100644
> --- a/gcc/c-family/c-attribs.c
> +++ b/gcc/c-family/c-attribs.c
> @@ -323,6 +323,8 @@ const struct attribute_spec c_common_attribute_table[] =
> attr_inline_exclusions },
> { "artificial", 0, 0, true, false, false, false,
> handle_artificial_attribute, NULL },
> + { "inline_ignore_target", 0, 0, true, false, false, false,
> + handle_artificial_attribute, NULL },
> { "flatten", 0, 0, true, false, false, false,
> handle_flatten_attribute, NULL },
> { "used", 0, 0, true, false, false, false,
> diff --git a/gcc/common/config/i386/i386-common.c
> b/gcc/common/config/i386/i386-common.c
> index b89183b830e..5caa53ac93f 100644
> --- a/gcc/common/config/i386/i386-common.c
> +++ b/gcc/common/config/i386/i386-common.c
> @@ -29,303 +29,6 @@ along with GCC; see the file COPYING3. If not see
> #include "opts.h"
> #include "flags.h"
>
> -/* Define a set of ISAs which are available when a given ISA is
> - enabled. MMX and SSE ISAs are handled separately. */
> -
> -#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
> -#define OPTION_MASK_ISA_3DNOW_SET \
> - (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
> -#define OPTION_MASK_ISA_3DNOW_A_SET \
> - (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
> -
> -#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
> -#define OPTION_MASK_ISA_SSE2_SET \
> - (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
> -#define OPTION_MASK_ISA_SSE3_SET \
> - (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
> -#define OPTION_MASK_ISA_SSSE3_SET \
> - (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
> -#define OPTION_MASK_ISA_SSE4_1_SET \
> - (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
> -#define OPTION_MASK_ISA_SSE4_2_SET \
> - (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
> -#define OPTION_MASK_ISA_AVX_SET \
> - (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
> - | OPTION_MASK_ISA_XSAVE_SET)
> -#define OPTION_MASK_ISA_FMA_SET \
> - (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
> -#define OPTION_MASK_ISA_AVX2_SET \
> - (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
> -#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
> -#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
> -#define OPTION_MASK_ISA_XSAVEOPT_SET \
> - (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
> -#define OPTION_MASK_ISA_AVX512F_SET \
> - (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
> -#define OPTION_MASK_ISA_AVX512CD_SET \
> - (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512PF_SET \
> - (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512ER_SET \
> - (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512DQ_SET \
> - (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512BW_SET \
> - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512VL_SET \
> - (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512IFMA_SET \
> - (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512VBMI_SET \
> - (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
> -#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
> -#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
> -#define OPTION_MASK_ISA_AVX512VBMI2_SET \
> - (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512VNNI_SET \
> - (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
> -#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
> - (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA_AVX512BITALG_SET \
> - (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
> -#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
> -#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
> -#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
> -#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
> -#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
> -#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
> -#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
> -#define OPTION_MASK_ISA_XSAVES_SET \
> - (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
> -#define OPTION_MASK_ISA_XSAVEC_SET \
> - (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
> -#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
> -#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET
> OPTION_MASK_ISA2_AVX512VP2INTERSECT
> -#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
> -#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8
> -#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16
> -
> -/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
> - as -msse4.2. */
> -#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
> -
> -#define OPTION_MASK_ISA_SSE4A_SET \
> - (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
> -#define OPTION_MASK_ISA_FMA4_SET \
> - (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
> - | OPTION_MASK_ISA_AVX_SET)
> -#define OPTION_MASK_ISA_XOP_SET \
> - (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
> -#define OPTION_MASK_ISA_LWP_SET \
> - OPTION_MASK_ISA_LWP
> -
> -/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
> -#define OPTION_MASK_ISA_AES_SET \
> - (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
> -#define OPTION_MASK_ISA_SHA_SET \
> - (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
> -#define OPTION_MASK_ISA_PCLMUL_SET \
> - (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
> -
> -#define OPTION_MASK_ISA_ABM_SET \
> - (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
> -
> -#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
> -#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
> -#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
> -#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
> -#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
> -#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
> -#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
> -#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
> -#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
> -#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
> -#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
> -#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
> -
> -#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
> -#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
> -#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
> -#define OPTION_MASK_ISA_F16C_SET \
> - (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
> -#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
> -#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
> -#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
> -#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
> -#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
> -#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
> -#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
> -#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
> -#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
> -#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
> -#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
> -#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
> -#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
> -#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
> -#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
> -#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
> -#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
> -#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
> -#define OPTION_MASK_ISA2_WIDEKL_SET \
> - (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
> -
> -/* Define a set of ISAs which aren't available when a given ISA is
> - disabled. MMX and SSE ISAs are handled separately. */
> -
> -#define OPTION_MASK_ISA_MMX_UNSET \
> - (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
> -#define OPTION_MASK_ISA_3DNOW_UNSET \
> - (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
> -#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
> -
> -#define OPTION_MASK_ISA_SSE_UNSET \
> - (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
> -#define OPTION_MASK_ISA_SSE2_UNSET \
> - (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
> -#define OPTION_MASK_ISA_SSE3_UNSET \
> - (OPTION_MASK_ISA_SSE3 \
> - | OPTION_MASK_ISA_SSSE3_UNSET \
> - | OPTION_MASK_ISA_SSE4A_UNSET )
> -#define OPTION_MASK_ISA_SSSE3_UNSET \
> - (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
> -#define OPTION_MASK_ISA_SSE4_1_UNSET \
> - (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
> -#define OPTION_MASK_ISA_SSE4_2_UNSET \
> - (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
> -#define OPTION_MASK_ISA_AVX_UNSET \
> - (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
> - | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
> - | OPTION_MASK_ISA_AVX2_UNSET )
> -#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
> -#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
> -#define OPTION_MASK_ISA_XSAVE_UNSET \
> - (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
> - | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
> - | OPTION_MASK_ISA_AVX_UNSET)
> -#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET
> -#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
> -#define OPTION_MASK_ISA_AVX2_UNSET \
> - (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
> -#define OPTION_MASK_ISA2_AVX2_UNSET \
> - (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
> -#define OPTION_MASK_ISA_AVX512F_UNSET \
> - (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
> - | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
> - | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
> - | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
> - | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
> - | OPTION_MASK_ISA_AVX512VNNI_UNSET \
> - | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
> - | OPTION_MASK_ISA_AVX512BITALG_UNSET)
> -#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
> -#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
> -#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
> -#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
> -#define OPTION_MASK_ISA_AVX512BW_UNSET \
> - (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
> -#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
> -#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
> -#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
> -#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
> -#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
> -#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
> -#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
> -#define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
> -#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
> -#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
> -#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
> -#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
> -#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
> -#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
> -#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
> -#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
> -#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
> -#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
> -#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
> -#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
> -#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
> -#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
> -#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
> -#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
> -#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
> -#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
> -#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
> -#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
> -#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
> -#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
> -#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
> -#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
> -#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
> -#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
> -#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET
> OPTION_MASK_ISA2_AVX512VP2INTERSECT
> -#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
> -#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE
> -#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
> -#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
> -#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
> -#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
> -#define OPTION_MASK_ISA2_KL_UNSET \
> - (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
> -#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
> -
> -/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
> - as -mno-sse4.1. */
> -#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
> -
> -#define OPTION_MASK_ISA_SSE4A_UNSET \
> - (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
> -
> -#define OPTION_MASK_ISA_FMA4_UNSET \
> - (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
> -#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
> -#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
> -
> -#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
> -#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
> -#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
> -#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
> -#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
> -#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
> -#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
> -#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
> -#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
> -#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
> -#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
> -#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
> -#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
> -#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
> -#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
> -#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
> -
> -#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
> -#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
> -#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
> -#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
> -
> -#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
> - (OPTION_MASK_ISA_MMX_UNSET \
> - | OPTION_MASK_ISA_SSE_UNSET)
> -
> -#define OPTION_MASK_ISA2_AVX512F_UNSET \
> - (OPTION_MASK_ISA2_AVX512BF16_UNSET \
> - | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
> - | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
> - | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
> -#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
> - (OPTION_MASK_ISA2_AVX512F_UNSET)
> -#define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
> -#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
> -#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
> -#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
> -#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
> -#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
> -#define OPTION_MASK_ISA2_SSE2_UNSET \
> - (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
> -#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
> -
> -#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET
> -
> /* Set 1 << value as value of -malign-FLAG option. */
>
> static void
> diff --git a/gcc/common/config/i386/i386-common.h
> b/gcc/common/config/i386/i386-common.h
> new file mode 100644
> index 00000000000..4a7fd290bcf
> --- /dev/null
> +++ b/gcc/common/config/i386/i386-common.h
> @@ -0,0 +1,315 @@
> +/* IA-32 common macros.
> + Copyright (C) 2021 Free Software Foundation, Inc.
> +
> +This file is part of GCC.
> +
> +GCC is free software; you can redistribute it and/or modify
> +it under the terms of the GNU General Public License as published by
> +the Free Software Foundation; either version 3, or (at your option)
> +any later version.
> +
> +GCC is distributed in the hope that it will be useful,
> +but WITHOUT ANY WARRANTY; without even the implied warranty of
> +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +GNU General Public License for more details.
> +
> +You should have received a copy of the GNU General Public License
> +along with GCC; see the file COPYING3. If not see
> +<http://www.gnu.org/licenses/>. */
> +
> +/* Define a set of ISAs which are available when a given ISA is
> + enabled. MMX and SSE ISAs are handled separately. */
> +
> +#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
> +#define OPTION_MASK_ISA_3DNOW_SET \
> + (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
> +#define OPTION_MASK_ISA_3DNOW_A_SET \
> + (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
> +
> +#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
> +#define OPTION_MASK_ISA_SSE2_SET \
> + (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
> +#define OPTION_MASK_ISA_SSE3_SET \
> + (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
> +#define OPTION_MASK_ISA_SSSE3_SET \
> + (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
> +#define OPTION_MASK_ISA_SSE4_1_SET \
> + (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
> +#define OPTION_MASK_ISA_SSE4_2_SET \
> + (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
> +#define OPTION_MASK_ISA_AVX_SET \
> + (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
> + | OPTION_MASK_ISA_XSAVE_SET)
> +#define OPTION_MASK_ISA_FMA_SET \
> + (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
> +#define OPTION_MASK_ISA_AVX2_SET \
> + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
> +#define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
> +#define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
> +#define OPTION_MASK_ISA_XSAVEOPT_SET \
> + (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
> +#define OPTION_MASK_ISA_AVX512F_SET \
> + (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
> +#define OPTION_MASK_ISA_AVX512CD_SET \
> + (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512PF_SET \
> + (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512ER_SET \
> + (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512DQ_SET \
> + (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512BW_SET \
> + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512VL_SET \
> + (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512IFMA_SET \
> + (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512VBMI_SET \
> + (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
> +#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
> +#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
> +#define OPTION_MASK_ISA_AVX512VBMI2_SET \
> + (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512VNNI_SET \
> + (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
> +#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
> + (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA_AVX512BITALG_SET \
> + (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
> +#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
> +#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
> +#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
> +#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
> +#define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
> +#define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
> +#define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
> +#define OPTION_MASK_ISA_XSAVES_SET \
> + (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
> +#define OPTION_MASK_ISA_XSAVEC_SET \
> + (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
> +#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
> +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET
> OPTION_MASK_ISA2_AVX512VP2INTERSECT
> +#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
> +#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8
> +#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16
> +
> +/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
> + as -msse4.2. */
> +#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
> +
> +#define OPTION_MASK_ISA_SSE4A_SET \
> + (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
> +#define OPTION_MASK_ISA_FMA4_SET \
> + (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
> + | OPTION_MASK_ISA_AVX_SET)
> +#define OPTION_MASK_ISA_XOP_SET \
> + (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
> +#define OPTION_MASK_ISA_LWP_SET \
> + OPTION_MASK_ISA_LWP
> +
> +/* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
> +#define OPTION_MASK_ISA_AES_SET \
> + (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
> +#define OPTION_MASK_ISA_SHA_SET \
> + (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
> +#define OPTION_MASK_ISA_PCLMUL_SET \
> + (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
> +
> +#define OPTION_MASK_ISA_ABM_SET \
> + (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
> +
> +#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
> +#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
> +#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
> +#define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
> +#define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
> +#define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
> +#define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
> +#define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
> +#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
> +#define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
> +#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
> +#define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
> +
> +#define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
> +#define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
> +#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
> +#define OPTION_MASK_ISA_F16C_SET \
> + (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
> +#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
> +#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
> +#define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
> +#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
> +#define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
> +#define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
> +#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
> +#define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
> +#define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
> +#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
> +#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
> +#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
> +#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
> +#define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
> +#define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
> +#define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
> +#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
> +#define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
> +#define OPTION_MASK_ISA2_WIDEKL_SET \
> + (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
> +
> +/* Define a set of ISAs which aren't available when a given ISA is
> + disabled. MMX and SSE ISAs are handled separately. */
> +
> +#define OPTION_MASK_ISA_MMX_UNSET \
> + (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
> +#define OPTION_MASK_ISA_3DNOW_UNSET \
> + (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
> +#define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
> +
> +#define OPTION_MASK_ISA_SSE_UNSET \
> + (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
> +#define OPTION_MASK_ISA_SSE2_UNSET \
> + (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
> +#define OPTION_MASK_ISA_SSE3_UNSET \
> + (OPTION_MASK_ISA_SSE3 \
> + | OPTION_MASK_ISA_SSSE3_UNSET \
> + | OPTION_MASK_ISA_SSE4A_UNSET )
> +#define OPTION_MASK_ISA_SSSE3_UNSET \
> + (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
> +#define OPTION_MASK_ISA_SSE4_1_UNSET \
> + (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
> +#define OPTION_MASK_ISA_SSE4_2_UNSET \
> + (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
> +#define OPTION_MASK_ISA_AVX_UNSET \
> + (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
> + | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
> + | OPTION_MASK_ISA_AVX2_UNSET )
> +#define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
> +#define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
> +#define OPTION_MASK_ISA_XSAVE_UNSET \
> + (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
> + | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
> + | OPTION_MASK_ISA_AVX_UNSET)
> +#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET
> +#define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
> +#define OPTION_MASK_ISA_AVX2_UNSET \
> + (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
> +#define OPTION_MASK_ISA2_AVX2_UNSET \
> + (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
> +#define OPTION_MASK_ISA_AVX512F_UNSET \
> + (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
> + | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
> + | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
> + | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
> + | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
> + | OPTION_MASK_ISA_AVX512VNNI_UNSET \
> + | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
> + | OPTION_MASK_ISA_AVX512BITALG_UNSET)
> +#define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
> +#define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
> +#define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
> +#define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
> +#define OPTION_MASK_ISA_AVX512BW_UNSET \
> + (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
> +#define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
> +#define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
> +#define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
> +#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
> +#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
> +#define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
> +#define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
> +#define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
> +#define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
> +#define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
> +#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
> +#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
> +#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
> +#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
> +#define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
> +#define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
> +#define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
> +#define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
> +#define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
> +#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
> +#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
> +#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
> +#define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
> +#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
> +#define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
> +#define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
> +#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
> +#define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
> +#define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
> +#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
> +#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
> +#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
> +#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
> +#define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
> +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET
> OPTION_MASK_ISA2_AVX512VP2INTERSECT
> +#define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
> +#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE
> +#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
> +#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
> +#define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
> +#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
> +#define OPTION_MASK_ISA2_KL_UNSET \
> + (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
> +#define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
> +
> +/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
> + as -mno-sse4.1. */
> +#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
> +
> +#define OPTION_MASK_ISA_SSE4A_UNSET \
> + (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
> +
> +#define OPTION_MASK_ISA_FMA4_UNSET \
> + (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
> +#define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
> +#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
> +
> +#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
> +#define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
> +#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
> +#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
> +#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
> +#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
> +#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
> +#define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
> +#define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
> +#define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
> +#define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
> +#define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
> +#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
> +#define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
> +#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
> +#define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
> +
> +#define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
> +#define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
> +#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
> +#define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
> +
> +#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
> + (OPTION_MASK_ISA_MMX_UNSET \
> + | OPTION_MASK_ISA_SSE_UNSET)
> +
> +#define OPTION_MASK_ISA2_AVX512F_UNSET \
> + (OPTION_MASK_ISA2_AVX512BF16_UNSET \
> + | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
> + | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
> + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
> +#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
> + (OPTION_MASK_ISA2_AVX512F_UNSET)
> +#define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
> +#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
> +#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
> +#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
> +#define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
> +#define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
> +#define OPTION_MASK_ISA2_SSE2_UNSET \
> + (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
> +#define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
> +
> +#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 7c41302c75b..aec6b224962 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -553,7 +553,7 @@ ix86_can_inline_p (tree caller, tree callee)
>
> /* Changes of those flags can be tolerated for always inlines. Lets hope
> user knows what he is doing. */
> - const unsigned HOST_WIDE_INT always_inline_safe_mask
> + unsigned HOST_WIDE_INT always_inline_safe_mask
> = (MASK_USE_8BIT_IDIV | MASK_ACCUMULATE_OUTGOING_ARGS
> | MASK_NO_ALIGN_STRINGOPS | MASK_AVX256_SPLIT_UNALIGNED_LOAD
> | MASK_AVX256_SPLIT_UNALIGNED_STORE | MASK_CLD
> @@ -578,14 +578,45 @@ ix86_can_inline_p (tree caller, tree callee)
> && lookup_attribute ("always_inline",
> DECL_ATTRIBUTES (callee)));
>
> + /* Ignore target non-integer option mismatch if callee has
> + inline_ignore_target attribute. */
> + bool inline_ignore_target
> + = lookup_attribute ("inline_ignore_target",
> + DECL_ATTRIBUTES (callee));
> +
> cgraph_node *callee_node = cgraph_node::get (callee);
> +
> + if (inline_ignore_target)
> + {
> + /* If target vector option mismatch can be ignored, callee's
> + integer ISA options should be a subset of the caller's
> + integer ISA options. */
> + always_inline_safe_mask |= MASK_80387;
> + HOST_WIDE_INT callee_integer_isa_flags
> + = (callee_opts->x_ix86_isa_flags
> + & ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET);
> + HOST_WIDE_INT callee_integer_isa_flags2
> + = (callee_opts->x_ix86_isa_flags2
> + & ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET);
> + if (((caller_opts->x_ix86_isa_flags
> + & callee_integer_isa_flags)
> + != callee_integer_isa_flags)
> + || ((caller_opts->x_ix86_isa_flags2
> + & callee_integer_isa_flags2)
> + != callee_integer_isa_flags2))
> + return false;
> + }
> +
> /* Callee's isa options should be a subset of the caller's, i.e. a SSE4
> function can inline a SSE2 function but a SSE2 function can't inline
> a SSE4 function. */
> - if (((caller_opts->x_ix86_isa_flags & callee_opts->x_ix86_isa_flags)
> - != callee_opts->x_ix86_isa_flags)
> - || ((caller_opts->x_ix86_isa_flags2 & callee_opts->x_ix86_isa_flags2)
> - != callee_opts->x_ix86_isa_flags2))
> + if (!inline_ignore_target
> + && (((caller_opts->x_ix86_isa_flags
> + & callee_opts->x_ix86_isa_flags)
> + != callee_opts->x_ix86_isa_flags)
> + || ((caller_opts->x_ix86_isa_flags2
> + & callee_opts->x_ix86_isa_flags2)
> + != callee_opts->x_ix86_isa_flags2)))
> ret = false;
>
> /* See if we have the same non-isa options. */
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index b4001d21b70..c07bd987fc9 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2569,6 +2569,7 @@ constexpr wide_int_bitmask PTA_KNM = PTA_KNL |
> PTA_AVX5124VNNIW
>
> #include "insn-attr-common.h"
>
> +#include "common/config/i386/i386-common.h"
> #include "common/config/i386/i386-cpuinfo.h"
>
> class pta
> diff --git a/gcc/config/i386/ia32intrin.h b/gcc/config/i386/ia32intrin.h
> index 591394076cc..04ed74ed01e 100644
> --- a/gcc/config/i386/ia32intrin.h
> +++ b/gcc/config/i386/ia32intrin.h
> @@ -107,12 +107,24 @@ __rdpmc (int __S)
> #endif /* __iamcu__ */
>
> /* rdtsc */
> -#define __rdtsc() __builtin_ia32_rdtsc ()
> +extern __inline unsigned long long
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__,
> + __inline_ignore_target__))
> +__rdtsc (void)
> +{
> + return __builtin_ia32_rdtsc ();
> +}
>
> #ifndef __iamcu__
>
> /* rdtscp */
> -#define __rdtscp(a) __builtin_ia32_rdtscp (a)
> +extern __inline unsigned long long
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__,
> + __inline_ignore_target__))
> +__rdtscp (unsigned int *__A)
> +{
> + return __builtin_ia32_rdtscp (__A);
> +}
>
> #endif /* __iamcu__ */
>
> diff --git a/gcc/config/i386/serializeintrin.h
> b/gcc/config/i386/serializeintrin.h
> index e280250b198..d990d310b75 100644
> --- a/gcc/config/i386/serializeintrin.h
> +++ b/gcc/config/i386/serializeintrin.h
> @@ -34,7 +34,13 @@
> #define __DISABLE_SERIALIZE__
> #endif /* __SERIALIZE__ */
>
> -#define _serialize() __builtin_ia32_serialize ()
> +extern __inline void
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__,
> + __inline_ignore_target__))
> +_serialize (void)
> +{
> + __builtin_ia32_serialize ();
> +}
>
> #ifdef __DISABLE_SERIALIZE__
> #undef __DISABLE_SERIALIZE__
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 849c8802473..a29ebd3f456 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -3187,6 +3187,14 @@ int S::interface (int) __attribute__ ((ifunc
> ("_ZN1S8resolverEv")));
> Indirect functions cannot be weak. Binutils version 2.20.1 or higher
> and GNU C Library version 2.11.1 are required to use this feature.
>
> +@item inline_ignore_target
> +@cindex @code{inline_ignore_target} function attribute
> +The @code{inline_ignore_target} attribute on functions is used to
> +inform the compiler that target specific option mismatch on functions
> +with the @code{always_inline} attribute may be ignored. On x86 targets,
> +this attribute can be used on integer functions to ignore target
> +non-integer option mismatch.
> +
> @item interrupt
> @itemx interrupt_handler
> Many GCC back ends support attributes to indicate that a function is
> diff --git a/gcc/testsuite/gcc.target/i386/pr99744-3.c
> b/gcc/testsuite/gcc.target/i386/pr99744-3.c
> new file mode 100644
> index 00000000000..5b6b1c20af7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr99744-3.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +#include <x86intrin.h>
> +
> +__attribute__ ((target("general-regs-only")))
> +void
> +foo1 (void)
> +{
> + _serialize ();
> +}
> +
> +/* { dg-error "target specific option mismatch" "" { target *-*-* } 0 } */
> --
> 2.30.2
>
