On Tue, Apr 13, 2021 at 6:38 PM Uros Bizjak <ubiz...@gmail.com> wrote: > > On Tue, Apr 13, 2021 at 12:18 PM Hongtao Liu <crazy...@gmail.com> wrote: > > > > Hi: > > As described in PR, we introduced tigerlake string in driver-i386.c > > by r9-8652 w/o support -march/tune=tigerlake which causes an error > > when using -march/tune=native with GCC9 on tigerlake machine. > > Bootstrapped and regtested on x86-64_iinux-gnu{-m32,}. > > Ok for GCC9? > > > > gcc/ > > * common/config/i386/i386-common.c > > (processor_names): Add tigerlake. > > (processor_alias_table): Ditto. > > * config.gcc: Document -march=tigerlake. > > Nope. Better. > > (x86_64_archs): Ditto. > > > * config/i386/driver-i386.c > > (host_detect_local_cpu): Detect tigerlake, add "has_avx" to > > classify processor. > > * config/i386/i386-c.c (ix86_target_macros_internal): Handle > > tigerlake. > > Handle PROCESSOR_TIGERLAKE. > > > * config/i386/i386.c (m_TIGERLAKE) : Define. > > (m_CORE_AVX512): Ditto. > > You don't define this macro, but you add m_TIGERLAKE to m_CORE_AVX512. > Please correct this confusion. > > > (processor_cost_table): Add tigerlake. > > Please correct the above. You added skylake_cost. > > > (ix86_option_override_internal): Handle PTA_MOVDIRI, PTA_MOVDIR64B. > > Where? > > > (processor_model): Add M_INTEL_COREI7_TIGERLAKE. > > (arch_names_table): Add tigerlake. > > (get_builtin_code_for_version) : Handle PROCESSOR_TIGERLAKE. > > * config/i386/i386.h (TARGET_TIGERLAKE): Define. > > (processor_type) : Add PROCESSOR_TIGERLAKE. > > (enum processor_type) > > > (PTA_TIGERLAKE) : Ditto. > > Ditto what? This is a new define. > > > * doc/extend.texi: Add tigerlake. > > * doc/invoke.texi: Add tigerlake. > > Added where? To which section? > > > gcc/testsuite/ > > * gcc.target/i386/funcspec-56.inc: Handle new march. > > * g++.target/i386/mv16.C: Handle new march > > Dot. > > > > > libgcc/ > > * config/i386/cpuinfo.h: Add INTEL_COREI7_TIGERLAKE. > > (enum processor_subtypes) > > > > From-SVN: r274693 > > Please repost with improved/corrected ChangeLog. > > Uros. > > > -- > > BR, > > Hongtao
updated. gcc/ * common/config/i386/i386-common.c (processor_names): Add tigerlake. (processor_alias_table): Ditto. * config.gcc (x86_64_archs): Ditto. * config/i386/driver-i386.c (host_detect_local_cpu): Detect tigerlake, add "has_avx" to classify processor. * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_TIGERLAKE. * config/i386/i386.c (m_TIGERLAKE): Define. (m_CORE_AVX512): Add m_TIGERLAKE. (processor_cost_table): Add skylake_cost for tigerlake. (processor_model): Add M_INTEL_COREI7_TIGERLAKE. (arch_names_table): Add tigerlake. (get_builtin_code_for_version): Handle PROCESSOR_TIGERLAKE. * config/i386/i386.h (TARGET_TIGERLAKE): Define. (enum processor_type): Add PROCESSOR_TIGERLAKE. (PTA_TIGERLAKE): Define. * doc/extend.texi (__builtin_cpu_is): Add tigerlake. * doc/invoke.texi (-march=cpu-type): Ditto. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march. libgcc/ * config/i386/cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_TIGERLAKE. -- BR, Hongtao
From 0ab46895773076c388aa7aca34345041cd2ff694 Mon Sep 17 00:00:00 2001 From: Hongtao Liu <liuho...@gcc.gnu.org> Date: Tue, 20 Aug 2019 07:06:03 +0000 Subject: [PATCH] backport TIGERLAKE part to GCC9. 2019-08-20 Lili Cui <lili....@intel.com> gcc/ * common/config/i386/i386-common.c (processor_names): Add tigerlake. (processor_alias_table): Ditto. * config.gcc (x86_64_archs): Ditto. * config/i386/driver-i386.c (host_detect_local_cpu): Detect tigerlake, add "has_avx" to classify processor. * config/i386/i386-c.c (ix86_target_macros_internal): Handle PROCESSOR_TIGERLAKE. * config/i386/i386.c (m_TIGERLAKE): Define. (m_CORE_AVX512): Add m_TIGERLAKE. (processor_cost_table): Add skylake_cost for tigerlake. (processor_model): Add M_INTEL_COREI7_TIGERLAKE. (arch_names_table): Add tigerlake. (get_builtin_code_for_version): Handle PROCESSOR_TIGERLAKE. * config/i386/i386.h (TARGET_TIGERLAKE): Define. (enum processor_type): Add PROCESSOR_TIGERLAKE. (PTA_TIGERLAKE): Define. * doc/extend.texi (__builtin_cpu_is): Add tigerlake. * doc/invoke.texi (-march=cpu-type): Ditto. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.target/i386/mv16.C: Handle new march. libgcc/ * config/i386/cpuinfo.h (enum processor_subtypes): Add INTEL_COREI7_TIGERLAKE. From-SVN: r274693 --- gcc/common/config/i386/i386-common.c | 2 + gcc/config.gcc | 3 +- gcc/config/i386/driver-i386.c | 62 ++++++++++--------- gcc/config/i386/i386-c.c | 7 +++ gcc/config/i386/i386.c | 12 +++- gcc/config/i386/i386.h | 4 ++ gcc/doc/extend.texi | 3 + gcc/doc/invoke.texi | 8 +++ gcc/testsuite/g++.target/i386/mv16.C | 6 ++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 + libgcc/config/i386/cpuinfo.h | 1 + 11 files changed, 78 insertions(+), 31 deletions(-) diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index c7841939e89..11960300bfc 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -1509,6 +1509,7 @@ const char *const processor_names[] = "icelake-client", "icelake-server", "cascadelake", + "tigerlake", "intel", "geode", "k6", @@ -1591,6 +1592,7 @@ const pta processor_alias_table[] = PTA_ICELAKE_SERVER}, {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL, PTA_CASCADELAKE}, + {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL}, {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT}, diff --git a/gcc/config.gcc b/gcc/config.gcc index 82f80d4c748..94885c7d758 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -667,7 +667,8 @@ bdver3 bdver4 znver1 znver2 btver1 btver2 k8 k8-sse3 opteron \ opteron-sse3 nocona core2 corei7 corei7-avx core-avx-i core-avx2 atom \ slm nehalem westmere sandybridge ivybridge haswell broadwell bonnell \ silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \ -skylake goldmont goldmont-plus tremont cascadelake x86-64 native" +skylake goldmont goldmont-plus tremont cascadelake tigerlake x86-64 \ +native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index db8b4fa8aab..26c1ec1fda9 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -885,36 +885,42 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (arch) { /* This is unknown family 0x6 CPU. */ - /* Assume Ice Lake Server. */ - if (has_wbnoinvd) - cpu = "icelake-server"; - /* Assume Ice Lake. */ - else if (has_gfni) - cpu = "icelake-client"; - /* Assume Cannon Lake. */ - else if (has_avx512vbmi) - cpu = "cannonlake"; - /* Assume Knights Mill. */ - else if (has_avx5124vnniw) - cpu = "knm"; - /* Assume Knights Landing. */ - else if (has_avx512er) - cpu = "knl"; - /* Assume Skylake with AVX-512. */ - else if (has_avx512f) - cpu = "skylake-avx512"; - /* Assume Skylake. */ - else if (has_clflushopt) - cpu = "skylake"; - /* Assume Broadwell. */ - else if (has_adx) - cpu = "broadwell"; - else if (has_avx2) + if (has_avx) + { + /* Assume Ice Lake Server. */ + if (has_wbnoinvd) + cpu = "icelake-server"; + /* Assume Ice Lake. */ + else if (has_avx512bitalg) + cpu = "icelake-client"; + /* Assume Tiger Lake */ + else if (has_movdiri) + cpu = "tigerlake"; + /* Assume Cannon Lake. */ + else if (has_avx512vbmi) + cpu = "cannonlake"; + /* Assume Knights Mill. */ + else if (has_avx5124vnniw) + cpu = "knm"; + /* Assume Knights Landing. */ + else if (has_avx512er) + cpu = "knl"; + /* Assume Skylake with AVX-512. */ + else if (has_avx512f) + cpu = "skylake-avx512"; + /* Assume Skylake. */ + else if (has_clflushopt) + cpu = "skylake"; + /* Assume Broadwell. */ + else if (has_adx) + cpu = "broadwell"; + else if (has_avx2) /* Assume Haswell. */ - cpu = "haswell"; - else if (has_avx) + cpu = "haswell"; + else /* Assume Sandy Bridge. */ - cpu = "sandybridge"; + cpu = "sandybridge"; + } else if (has_sse4_2) { if (has_gfni) diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index f06fea1a8a5..ee74f2954cc 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -222,6 +222,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__cascadelake"); def_or_undef (parse_in, "__cascadelake__"); break; + case PROCESSOR_TIGERLAKE: + def_or_undef (parse_in, "__tigerlake"); + def_or_undef (parse_in, "__tigerlake__"); + break; /* use PROCESSOR_max to not set/unset the arch macro. */ case PROCESSOR_max: break; @@ -370,6 +374,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_CASCADELAKE: def_or_undef (parse_in, "__tune_cascadelake__"); break; + case PROCESSOR_TIGERLAKE: + def_or_undef (parse_in, "__tune_tigerlake__"); + break; case PROCESSOR_INTEL: case PROCESSOR_GENERIC: break; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 592455ef6d4..b0c90c28088 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -149,8 +149,10 @@ const struct processor_costs *ix86_cost = NULL; #define m_ICELAKE_CLIENT (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_CLIENT) #define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER) #define m_CASCADELAKE (HOST_WIDE_INT_1U<<PROCESSOR_CASCADELAKE) +#define m_TIGERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_TIGERLAKE) #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \ - | m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE) + | m_ICELAKE_CLIENT | m_ICELAKE_SERVER \ + | m_CASCADELAKE | m_TIGERLAKE) #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512) #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2) #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT) @@ -900,6 +902,7 @@ static const struct processor_costs *processor_cost_table[] = &skylake_cost, &skylake_cost, &skylake_cost, + &skylake_cost, &intel_cost, &geode_cost, &k6_cost, @@ -32012,7 +32015,8 @@ enum processor_model M_INTEL_COREI7_ICELAKE_CLIENT, M_INTEL_COREI7_ICELAKE_SERVER, M_AMDFAM17H_ZNVER2, - M_INTEL_COREI7_CASCADELAKE + M_INTEL_COREI7_CASCADELAKE, + M_INTEL_COREI7_TIGERLAKE, }; struct _arch_names_table @@ -32041,6 +32045,7 @@ static const _arch_names_table arch_names_table[] = {"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT}, {"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER}, {"cascadelake", M_INTEL_COREI7_CASCADELAKE}, + {"tigerlake", M_INTEL_COREI7_TIGERLAKE}, {"bonnell", M_INTEL_BONNELL}, {"silvermont", M_INTEL_SILVERMONT}, {"goldmont", M_INTEL_GOLDMONT}, @@ -32231,6 +32236,9 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) arg_str = "cascadelake"; priority = P_PROC_AVX512F; break; + case PROCESSOR_TIGERLAKE: + arg_str = "tigerlake"; + priority = P_PROC_AVX512F; case PROCESSOR_BONNELL: arg_str = "bonnell"; priority = P_PROC_SSSE3; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index d138dfac05c..74199deae71 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -408,6 +408,7 @@ extern const struct processor_costs ix86_size_cost; #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) #define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE) +#define TARGET_TIGERLAKE (ix86_tune == PROCESSOR_TIGERLAKE) #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) @@ -2282,6 +2283,7 @@ enum processor_type PROCESSOR_ICELAKE_CLIENT, PROCESSOR_ICELAKE_SERVER, PROCESSOR_CASCADELAKE, + PROCESSOR_TIGERLAKE, PROCESSOR_INTEL, PROCESSOR_GEODE, PROCESSOR_K6, @@ -2410,6 +2412,8 @@ const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | PTA_RDPID | PTA_AVX512VPOPCNTDQ; const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB; +const wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI + | PTA_MOVDIR64B | PTA_CLWB; const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 3ab83a1cf94..16ecd15273b 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21497,6 +21497,9 @@ Intel Core i7 Ice Lake Server CPU. @item cascadelake Intel Core i7 Cascadelake CPU. +@item tigerlake +Intel Core i7 Tigerlake CPU. + @item bonnell Intel Atom Bonnell CPU. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c39efa0e33e..7b5f6e03d9f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -27383,6 +27383,14 @@ SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ, AVX512CD and AVX512VNNI instruction set support. +@item tigerlake +Intel Tigerlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, +BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, +AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, AVX512IFMA, SHA, CLWB, UMIP, +RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ, AVX512BITALG, AVX512VNNI, VPCLMULQDQ, +VAES, PCONFIG, WBNOINVD, MOVDIRI, MOVDIR64B and CLWB instruction set support. + @item k6 AMD K6 CPU with MMX instruction set support. diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C index 81e15115f27..0b5a8c3e4a1 100644 --- a/gcc/testsuite/g++.target/i386/mv16.C +++ b/gcc/testsuite/g++.target/i386/mv16.C @@ -72,6 +72,10 @@ int __attribute__ ((target("arch=cascadelake"))) foo () { return 19; } +int __attribute__ ((target("arch=tigerlake"))) foo () { + return 20; +} + int main () { int val = foo (); @@ -100,6 +104,8 @@ int main () assert (val == 18); else if (__builtin_cpu_is ("cascadelake")) assert (val == 19); + else if (__builtin_cpu_is ("tigerlake")) + assert (val == 20); else assert (val == 0); diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index 0eb83a7fd30..898190b30e9 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -151,6 +151,7 @@ extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonl extern void test_arch_icelake_client (void) __attribute__((__target__("arch=icelake-client"))); extern void test_arch_icelake_server (void) __attribute__((__target__("arch=icelake-server"))); extern void test_arch_cascadelake (void) __attribute__((__target__("arch=cascadelake"))); +extern void test_arch_tigerlake (void) __attribute__((__target__("arch=tigerlake"))); extern void test_arch_k8 (void) __attribute__((__target__("arch=k8"))); extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3"))); extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron"))); diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h index b4492eb7eb4..4ba67932847 100644 --- a/libgcc/config/i386/cpuinfo.h +++ b/libgcc/config/i386/cpuinfo.h @@ -77,6 +77,7 @@ enum processor_subtypes INTEL_COREI7_ICELAKE_SERVER, AMDFAM17H_ZNVER2, INTEL_COREI7_CASCADELAKE, + INTEL_COREI7_TIGERLAKE, CPU_SUBTYPE_MAX }; -- 2.18.1