On Mon, 2021-04-26 at 09:36 -0700, Carl Love wrote: > Will, Segher: > > This patch adds the 128-bit integer support for divide, modulo, shift, > compare of 128-bit integers instructions and builtin support.
Hi, > > The patch has been tested on > powerpc64-linux instead (Power 8 BE) > powerpc64-linux instead (Power 9 LE) > powerpc64-linux instead (Power 10 LE) > > Please let me know if the patch is acceptable for mainline. > > Carl Love > > ----------------------------------------------------------- > > gcc/ChangeLog > > 2021-04-26 Carl Love <c...@us.ibm.com> > * config/rs6000/altivec.h (vec_dive, vec_mod): Add define for new > builtins. > * config/rs6000/altivec.md (UNSPEC_VMULEUD, UNSPEC_VMULESD, > UNSPEC_VMULOUD, UNSPEC_VMULOSD): New unspecs. > (altivec_eqv1ti, altivec_gtv1ti, altivec_gtuv1ti, altivec_vmuleud, > altivec_vmuloud, altivec_vmulesd, altivec_vmulosd, altivec_vrlq, > altivec_vrlqmi, altivec_vrlqmi_inst, altivec_vrlqnm, > altivec_vrlqnm_inst, altivec_vslq, altivec_vsrq, altivec_vsraq, > altivec_vcmpequt_p, altivec_vcmpgtst_p, altivec_vcmpgtut_p): New > define_insn. > (vec_widen_umult_even_v2di, vec_widen_smult_even_v2di, > vec_widen_umult_odd_v2di, vec_widen_smult_odd_v2di, altivec_vrlqmi, > altivec_vrlqnm): New define_expands. > * config/rs6000/rs6000-builtin.def (VCMPEQUT_P, VCMPGTST_P, > VCMPGTUT_P): Add macro expansions. > (BU_P10V_AV_P): Add builtin predicate definition. > (VCMPGTUT, VCMPGTST, VCMPEQUT, CMPNET, CMPGE_1TI, > CMPGE_U1TI, CMPLE_1TI, CMPLE_U1TI, VNOR_V1TI_UNS, VNOR_V1TI, VCMPNET_P, > VCMPAET_P, VMULEUD, VMULESD, VMULOUD, VMULOSD, VRLQ, > VSLQ, VSRQ, VSRAQ, VRLQNM, DIV_V1TI, UDIV_V1TI, DIVES_V1TI, DIVEU_V1TI, > MODS_V1TI, MODU_V1TI, VRLQMI): New macro expansions. > (VRLQ, VSLQ, VSRQ, VSRAQ, DIVE, MOD): New overload expansions. > * config/rs6000/rs6000-call.c (P10_BUILTIN_VCMPEQUT, > P10V_BUILTIN_CMPGE_1TI, P10V_BUILTIN_CMPGE_U1TI, > P10V_BUILTIN_VCMPGTUT, P10V_BUILTIN_VCMPGTST, > P10V_BUILTIN_CMPLE_1TI, P10V_BUILTIN_VCMPLE_U1TI, > P10V_BUILTIN_DIV_V1TI, P10V_BUILTIN_UDIV_V1TI, > P10V_BUILTIN_VMULESD, P10V_BUILTIN_VMULEUD, > P10V_BUILTIN_VMULOSD, P10V_BUILTIN_VMULOUD, > P10V_BUILTIN_VNOR_V1TI, P10V_BUILTIN_VNOR_V1TI_UNS, > P10V_BUILTIN_VRLQ, P10V_BUILTIN_VRLQMI, > P10V_BUILTIN_VRLQNM, P10V_BUILTIN_VSLQ, > P10V_BUILTIN_VSRQ, P10V_BUILTIN_VSRAQ, > P10V_BUILTIN_VCMPGTUT_P, P10V_BUILTIN_VCMPGTST_P, > P10V_BUILTIN_VCMPEQUT_P, P10V_BUILTIN_VCMPGTUT_P, > P10V_BUILTIN_VCMPGTST_P, P10V_BUILTIN_CMPNET, > P10V_BUILTIN_VCMPNET_P, P10V_BUILTIN_VCMPAET_P, > P10V_BUILTIN_DIVES_V1TI, P10V_BUILTIN_MODS_V1TI, > P10V_BUILTIN_MODU_V1TI): > New overloaded definitions. > (rs6000_gimple_fold_builtin) [P10V_BUILTIN_VCMPEQUT, > P10_BUILTIN_CMPNET, P10_BUILTIN_CMPGE_1TI, > P10_BUILTIN_CMPGE_U1TI, P10_BUILTIN_VCMPGTUT, > P10_BUILTIN_VCMPGTST, P10_BUILTIN_CMPLE_1TI, > P10_BUILTIN_CMPLE_U1TI]: New case statements. No signs of P10_BUILTIN_CMPNET below. possibly P10V_BUILTIN_CMPNET? S ame through at least P10_BUILTIN_CMPLE_U1TI. > (rs6000_init_builtins) [bool_V1TI_type_node, int_ftype_int_v1ti_v1ti]: > New assignments. > (altivec_init_builtins): New E_V1TImode case statement. > (builtin_function_type)[P10_BUILTIN_128BIT_VMULEUD, > P10_BUILTIN_128BIT_VMULOUD, P10_BUILTIN_128BIT_DIVEU_V1TI, > P10_BUILTIN_128BIT_MODU_V1TI, P10_BUILTIN_CMPGE_U1TI, > P10_BUILTIN_VCMPGTUT, P10_BUILTIN_VCMPEQUT]: New case statements. > * config/rs6000/r6000.c (rs6000_handle_altivec_attribute)[E_TImode, > E_V1TImode]: New case statements. > * config/rs6000/r6000.h (rs6000_builtin_type_index): New enum > value RS6000_BTI_bool_V1TI. > * config/rs6000/vector.md (vector_gtv1ti,vector_nltv1ti, > vector_gtuv1ti, vector_nltuv1ti, vector_ngtv1ti, vector_ngtuv1ti, > vector_eq_v1ti_p, vector_ne_v1ti_p, vector_ae_v1ti_p, > vector_gt_v1ti_p, vector_gtu_v1ti_p, vrotlv1ti3, vashlv1ti3, > vlshrv1ti3, vashrv1ti3): New define_expands. > * config/rs6000/vsx.md (UNSPEC_VSX_DIVSQ, UNSPEC_VSX_DIVUQ, > UNSPEC_VSX_DIVESQ, UNSPEC_VSX_DIVEUQ, UNSPEC_VSX_MODSQ, > UNSPEC_VSX_MODUQ): New unspecs. > (mulv2di3, vsx_div_v1ti, vsx_udiv_v1ti, vsx_dives_v1ti, > vsx_diveu_v1ti, vsx_mods_v1ti, vsx_modu_v1ti, xxswapd_v1ti): New > define_insns. > (vcmpnet): New define_expand. > * gcc/doc/extend.texi: Add documentation for the new builtins vec_rl, > vec_rlmi, vec_rlnm, vec_sl, vec_sr, vec_sra, vec_mule, vec_mulo, > vec_div, vec_dive, vec_mod, vec_cmpeq, vec_cmpne, vec_cmpgt, vec_cmplt, > vec_cmpge, vec_cmple, vec_all_eq, vec_all_ne, vec_all_gt, vec_all_lt, > vec_all_ge, vec_all_le, vec_any_eq, vec_any_ne, vec_any_gt, vec_any_lt, > vec_any_ge, vec_any_le. > > gcc/testsuite/ChangeLog > > 2021-04-26 Carl Love <c...@us.ibm.com> > * gcc.target/powerpc/int_128bit-runnable.c: New test file. ok. > --- > gcc/config/rs6000/altivec.h | 3 + > gcc/config/rs6000/altivec.md | 241 ++ > gcc/config/rs6000/rs6000-builtin.def | 48 +- > gcc/config/rs6000/rs6000-call.c | 136 +- > gcc/config/rs6000/rs6000.c | 1 + > gcc/config/rs6000/rs6000.h | 3 +- > gcc/config/rs6000/vector.md | 191 ++ > gcc/config/rs6000/vsx.md | 89 + I've skimmed those changes, nothing jumped out at me there. > gcc/doc/extend.texi | 171 ++ Only recommendation for extend.texi content is to spell out "result" instead of just "R". > .../gcc.target/powerpc/int_128bit-runnable.c | 2263 +++++++++++++++++ ok. Thanks -Will
