RE: [PATCH 4/9] arm: MVE: Factorize all vcmp* integer patterns

[Kyrylo Tkachov via Gcc-patches]

> -----Original Message-----
> From: Gcc-patches <gcc-patches-boun...@gcc.gnu.org> On Behalf Of
> Christophe Lyon via Gcc-patches
> Sent: 30 April 2021 15:10
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH 4/9] arm: MVE: Factorize all vcmp* integer patterns
> 
> After removing the signed and unsigned suffixes in the previous
> patches, we can now factorize the vcmp* patterns: there is no longer
> an asymmetry where operators do not have the same set of signed and
> unsigned variants.
> 
> The will make maintenance easier.

Ok.
Thanks,
Kyrill

> 
> MVE has a different set of vector comparison operators than Neon,
> so we have to introduce dedicated iterators.
> 
> 2021-03-01  Christophe Lyon  <christophe.l...@linaro.org>
> 
>       gcc/
>       * config/arm/iterators.md (MVE_COMPARISONS): New.
>       (mve_cmp_op): New.
>       (mve_cmp_type): New.
>       * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_<mode>): New,
> merge all
>       mve_vcmp patterns.
>       (mve_vcmpneq_<mode>, mve_vcmpcsq_n_<mode>,
> mve_vcmpcsq_<mode>)
>       (mve_vcmpeqq_n_<mode>, mve_vcmpeqq_<mode>,
> mve_vcmpgeq_n_<mode>)
>       (mve_vcmpgeq_<mode>, mve_vcmpgtq_n_<mode>,
> mve_vcmpgtq_<mode>)
>       (mve_vcmphiq_n_<mode>, mve_vcmphiq_<mode>,
> mve_vcmpleq_n_<mode>)
>       (mve_vcmpleq_<mode>, mve_vcmpltq_n_<mode>,
> mve_vcmpltq_<mode>)
>       (mve_vcmpneq_n_<mode>, mve_vcmpltq_n_<mode>,
> mve_vcmpltq_<mode>)
>       (mve_vcmpneq_n_<mode>): Remove.
> ---
>  gcc/config/arm/iterators.md |   8 ++
>  gcc/config/arm/mve.md       | 250 
> ++++----------------------------------------
>  2 files changed, 27 insertions(+), 231 deletions(-)
> 
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 0aba93f..29347f7 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -285,6 +285,8 @@ (define_code_iterator GTUGEU [gtu geu])
> 
>  ;; Comparisons for vc<cmp>
>  (define_code_iterator COMPARISONS [eq gt ge le lt])
> +;; Comparisons for MVE
> +(define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne])
> 
>  ;; A list of ...
>  (define_code_iterator IOR_XOR [ior xor])
> @@ -336,8 +338,14 @@ (define_code_attr arith_shift_insn
>  (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
>                            (gtu "gt") (geu "ge")])
> 
> +(define_code_attr mve_cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le 
> "le")
> +                              (gtu "hi") (geu "cs") (ne "ne")])
> +
>  (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
> 
> +(define_code_attr mve_cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")
> +                                (gtu "u") (geu "u") (ne "i")])
> +
>  (define_code_attr vfml_op [(plus "a") (minus "s")])
> 
>  (define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")])
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index e9f095d..40baff7 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -836,17 +836,30 @@ (define_insn "mve_vaddlvq_p_<supf>v4si"
>     (set_attr "length""8")])
> 
>  ;;
> -;; [vcmpneq_])
> +;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_,
> vcmpleq_, vcmpltq_])
>  ;;
> -(define_insn "mve_vcmpneq_<mode>"
> +(define_insn "mve_vcmp<mve_cmp_op>q_<mode>"
>    [
>     (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPNEQ))
> +     (MVE_COMPARISONS:HI (match_operand:MVE_2 1
> "s_register_operand" "w")
> +                 (match_operand:MVE_2 2 "s_register_operand" "w")))
> +  ]
> +  "TARGET_HAVE_MVE"
> +  "vcmp.<mve_cmp_type>%#<V_sz_elem>  <mve_cmp_op>, %q1, %q2"
> +  [(set_attr "type" "mve_move")
> +])
> +
> +;;
> +;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_,
> vcmpleq_n_, vcmpltq_n_, vcmpneq_n_])
> +;;
> +(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
> +  [
> +   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> +     (MVE_COMPARISONS:HI (match_operand:MVE_2 1
> "s_register_operand" "w")
> +                 (match_operand:<V_elem> 2 "s_register_operand" "r")))
>    ]
>    "TARGET_HAVE_MVE"
> -  "vcmp.i%#<V_sz_elem>  ne, %q1, %q2"
> +  "vcmp.<mve_cmp_type>%#<V_sz_elem>  <mve_cmp_op>, %q1, %2"
>    [(set_attr "type" "mve_move")
>  ])
> 
> @@ -1005,231 +1018,6 @@ (define_expand "cadd<rot><mode>3"
>  )
> 
>  ;;
> -;; [vcmpcsq_n_])
> -;;
> -(define_insn "mve_vcmpcsq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPCSQ_N_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.u%#<V_sz_elem>       cs, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpcsq_])
> -;;
> -(define_insn "mve_vcmpcsq_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPCSQ_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.u%#<V_sz_elem>       cs, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpeqq_n_])
> -;;
> -(define_insn "mve_vcmpeqq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPEQQ_N))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.i%#<V_sz_elem>       eq, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpeqq_])
> -;;
> -(define_insn "mve_vcmpeqq_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPEQQ))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.i%#<V_sz_elem>       eq, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpgeq_n_])
> -;;
> -(define_insn "mve_vcmpgeq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPGEQ_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       ge, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpgeq_])
> -;;
> -(define_insn "mve_vcmpgeq_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPGEQ_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       ge, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpgtq_n_])
> -;;
> -(define_insn "mve_vcmpgtq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPGTQ_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       gt, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpgtq_])
> -;;
> -(define_insn "mve_vcmpgtq_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPGTQ_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       gt, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmphiq_n_])
> -;;
> -(define_insn "mve_vcmphiq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPHIQ_N_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.u%#<V_sz_elem>       hi, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmphiq_])
> -;;
> -(define_insn "mve_vcmphiq_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPHIQ_U))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.u%#<V_sz_elem>       hi, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpleq_n_])
> -;;
> -(define_insn "mve_vcmpleq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPLEQ_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       le, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpleq_])
> -;;
> -(define_insn "mve_vcmpleq_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPLEQ_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       le, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpltq_n_])
> -;;
> -(define_insn "mve_vcmpltq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPLTQ_N_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       lt, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpltq_])
> -;;
> -(define_insn "mve_vcmpltq_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:MVE_2 2 "s_register_operand" "w")]
> -      VCMPLTQ_S))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.s%#<V_sz_elem>       lt, %q1, %q2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vcmpneq_n_])
> -;;
> -(define_insn "mve_vcmpneq_n_<mode>"
> -  [
> -   (set (match_operand:HI 0 "vpr_register_operand" "=Up")
> -     (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
> -                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
> -      VCMPNEQ_N))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vcmp.i%#<V_sz_elem>       ne, %q1, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
> -;;
>  ;; [veorq_u, veorq_s])
>  ;;
>  (define_insn "mve_veorq_u<mode>"
> --
> 2.7.4