Hi, Version 2 of this patch adds tests to verify the benefit of this change.
Ok for master? Thanks, Jonathan --- gcc/ChangeLog: 2021-06-14 Jonathan Wright <[email protected]> * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>): Change to an expander that emits the correct instruction depending on endianness. (aarch64_<sur><addsub>hn<mode>_insn_le): Define. (aarch64_<sur><addsub>hn<mode>_insn_be): Define. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_zero_high_half.c: Add new tests. From: Gcc-patches <[email protected]> on behalf of Jonathan Wright via Gcc-patches <[email protected]> Sent: 15 June 2021 11:02 To: [email protected] <[email protected]> Subject: [PATCH] aarch64: Model zero-high-half semantics of ADDHN/SUBHN instructions Hi, As subject, this patch models the zero-high-half semantics of the narrowing arithmetic Neon instructions in the aarch64_<sur><addsub>hn<mode> RTL pattern. Modeling these semantics allows for better RTL combinations while also removing some register allocation issues as the compiler now knows that the operation is totally destructive. Regression tested and bootstrapped on aarch64-none-linux-gnu - no issues. Ok for master? Thanks, Jonathan --- gcc/ChangeLog: 2021-06-14 Jonathan Wright <[email protected]> * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>): Change to an expander that emits the correct instruction depending on endianness. (aarch64_<sur><addsub>hn<mode>_insn_le): Define. (aarch64_<sur><addsub>hn<mode>_insn_be): Define.
rb14566.patch
Description: rb14566.patch
