On Thu, Jun 17, 2021 at 12:39:04PM -0500, Segher Boessenkool wrote:
> On Tue, Jun 08, 2021 at 08:21:25PM -0400, Michael Meissner wrote:
> > GCC will not convert ternary operations into using min/max instructions
> > provided in this patch unless the user uses -Ofast or similar switches due
> > to
> > issues with NaNs.
>
> It will not do it because it is *incorrect* to do :-)
>
> (The RTL operators smin/smax are undefined for any NaN inputs (unless
> both are the same bit pattern), and for different sign zeroes; it isn't
> only NaNs even).
>
> > gcc/
> > 2021-06-08 Michael Meissner <meiss...@linux.ibm.com>
> >
> > * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
> > 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
> > instructions.
>
> Please don't randomly break lines.
>
> > --- a/gcc/config/rs6000/rs6000.c
> > +++ b/gcc/config/rs6000/rs6000.c
> > @@ -16103,7 +16103,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code,
> > rtx op0, rtx op1)
> > /* VSX/altivec have direct min/max insns. */
> > if ((code == SMAX || code == SMIN)
> > && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
> > - || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
> > + || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
> > + || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
>
> The actual insns only check TARGET_POWER10 (so no TARGET_FLOAT128_HW).
> Which is right, this or that?
It should include TARGET_FLOAT128_HW. The problem area is a power10 running in
big endian mode and running 32-bit code. Because we don't have TImode, we
can't enable the IEEE 128-bit hardware instructions. And because we don't have
GLIBC support, we don't enable the FLOAT128 stuff by default on big endian.
> > +/* { dg-require-effective-target ppc_float128_hw } */
> > +/* { dg-require-effective-target power10_ok } */
> > +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
>
> In testcases we can assume that float128_hw is set whenever we have a
> p10; we don't manually disable it to make live hard for ourselves ;-)
Again, I put it in case somebody builds a BE power10 compiler.
> We could disallow disabling QP float separately from all other float.
> We will still need to test if float is enabled at all so it won't help
> all that much immediately, alas.
>
> With that TARGET_POWER10 condition fixed: okay for trunk, and for 11
> once it is tested for trunk on all systems. Thanks!
Thanks.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
