On Thu, Jun 24, 2021 at 10:44 AM liuhongt <hongtao....@intel.com> wrote:
>
> Still put general regs as first alloca order.
>
> This should fix 2 failures introduced by r12-1669, also add xfail to new
> failed testcases to temporarily avoid regression, eventually xfail should
> be removed.
>
> compare_test log on non-avx512 target
>
> Tests that now fail, but worked before (6 tests):
>
> gcc.target/i386/bitwise_mask_op-3.c scan-assembler-times kmovb[\t ] 4
> gcc.target/i386/bitwise_mask_op-3.c scan-assembler-times korb[\t ] 1
> gcc.target/i386/bitwise_mask_op-3.c scan-assembler-times kxorb[\t ] 1
> unix/-m32: gcc.target/i386/bitwise_mask_op-3.c scan-assembler-times kmovb[\t
> ] 4
> unix/-m32: gcc.target/i386/bitwise_mask_op-3.c scan-assembler-times korb[\t ]
> 1
> unix/-m32: gcc.target/i386/bitwise_mask_op-3.c scan-assembler-times kxorb[\t
> ] 1
>
> Tests that now work, but didn't before (2 tests):
>
> unix/-m32: gcc.target/i386/avx512bw-pr70329-1.c execution test
> unix/-m32: gcc.target/i386/pr96814.c execution test
>
> Bootstrap is ok, so is regression test on x86-64-linux-gnu{-m32,}.
> Ok for trunk?
Yes, let's start improvements from non-regressed state.
Thanks,
Uros.
> gcc/ChangeLog:
>
> PR target/101185
> * config/i386/i386.c (x86_order_regs_for_local_alloc):
> Revert r12-1669.
>
> gcc/testsuite/ChangeLog
>
> PR target/101185
> * gcc.target/i386/bitwise_mask_op-3.c: Add xfail to
> temporarily avoid regression, eventually xfail should be
> removed.
> ---
> gcc/config/i386/i386.c | 13 ++++---------
> gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c | 6 +++---
> 2 files changed, 7 insertions(+), 12 deletions(-)
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 3d5883b8d0e..c71c9e666a4 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -20476,15 +20476,6 @@ x86_order_regs_for_local_alloc (void)
> int pos = 0;
> int i;
>
> - /* When allocano cost of GENERAL_REGS is same as MASK_REGS, allocate
> - MASK_REGS first since it has already been disparaged. This is for
> - testcase bitwise_mask_op3.c where the input is allocated as mask
> - registers, then mask bitwise instructions should be used there.
> - Refer to pr101142. */
> - /* Mask register. */
> - for (i = FIRST_MASK_REG; i <= LAST_MASK_REG; i++)
> - reg_alloc_order [pos++] = i;
> -
> /* First allocate the local general purpose registers. */
> for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
> if (GENERAL_REGNO_P (i) && call_used_or_fixed_reg_p (i))
> @@ -20511,6 +20502,10 @@ x86_order_regs_for_local_alloc (void)
> for (i = FIRST_EXT_REX_SSE_REG; i <= LAST_EXT_REX_SSE_REG; i++)
> reg_alloc_order [pos++] = i;
>
> + /* Mask register. */
> + for (i = FIRST_MASK_REG; i <= LAST_MASK_REG; i++)
> + reg_alloc_order [pos++] = i;
> +
> /* x87 registers. */
> if (TARGET_SSE_MATH)
> for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
> diff --git a/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c
> b/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c
> index 4a9078615aa..352c49d6c6b 100644
> --- a/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c
> +++ b/gcc/testsuite/gcc.target/i386/bitwise_mask_op-3.c
> @@ -12,7 +12,7 @@ foo_orb (__m512i a, __m512i b)
> foo = m1 | m2;
> }
>
> -/* { dg-final { scan-assembler-times "korb\[\t \]" "1" } } */
> +/* { dg-final { scan-assembler-times "korb\[\t \]" "1" { xfail *-*-* } } }
> */
>
> void
> foo_xorb (__m512i a, __m512i b)
> @@ -22,7 +22,7 @@ foo_xorb (__m512i a, __m512i b)
> foo = m1 ^ m2;
> }
>
> -/* { dg-final { scan-assembler-times "kxorb\[\t \]" "1" } } */
> +/* { dg-final { scan-assembler-times "kxorb\[\t \]" "1" { xfail *-*-* } } }
> */
>
> void
> foo_andb (__m512i a, __m512i b)
> @@ -40,4 +40,4 @@ foo_andnb (__m512i a, __m512i b)
> foo = m1 & ~m2;
> }
>
> -/* { dg-final { scan-assembler-times "kmovb\[\t \]" "4"} } */
> +/* { dg-final { scan-assembler-times "kmovb\[\t \]" "4" { xfail *-*-* } } }
> */
> --
> 2.27.0
>
