On Fri, Jun 25, 2021 at 8:48 AM Richard Biener <rguent...@suse.de> wrote:
>
> On Thu, 24 Jun 2021, Uros Bizjak wrote:
>
> > On Thu, Jun 24, 2021 at 1:07 PM Richard Biener <rguent...@suse.de> wrote:
> >
> > > This addds SLP pattern recognition for the SSE3/AVX [v]addsubp{ds} v0, v1
> > > instructions which compute { v0[0] - v1[0], v0[1], + v1[1], ... }
> > > thus subtract, add alternating on lanes, starting with subtract.
> > >
> > > It adds a corresponding optab and direct internal function,
> > > vec_addsub$a3 and renames the existing i386 backend patterns to
> > > the new canonical name.
> > >
> > > The SLP pattern matches the exact alternating lane sequence rather
> > > than trying to be clever and anticipating incoming permutes - we
> > > could permute the two input vectors to the needed lane alternation,
> > > do the addsub and then permute the result vector back but that's
> > > only profitable in case the two input or the output permute will
> > > vanish - something Tamars refactoring of SLP pattern recog should
> > > make possible.
> >
> > Using the attached patch, I was also able to generate addsub for the
> > following testcase:
> >
> > float x[2], y[2], z[2];
> >
> > void foo ()
> > {
> > x[0] = y[0] - z[0];
> > x[1] = y[1] + z[1];
> > }
> >
> > vmovq y(%rip), %xmm0
> > vmovq z(%rip), %xmm1
> > vaddsubps %xmm1, %xmm0, %xmm0
> > vmovlps %xmm0, x(%rip)
> > ret
>
> Nice. But I suppose it can be merged with the other now single
> pattern?
Actually, MMX_WITH_SSE V2SF modes do not support memory operands (they
operate on V2SF subreg of V4SF SSE registers), so a new mode attribute
would be needed to instantiate register operand in case of V2SF.
Uros.
>
> Richard.
