Add additional checks to verify destination[source] of a load[store] instruction is a register.
Modified code based on review comment to not change general logic of the flow. Braces needed on inner if-else to prevent error during bootstrap for ambiguous 'else'. Bootstrap/regtest on powerpc64le with no new regressions. Ok for master? -Pat 2021-08-07 Pat Haugen <pthau...@linux.ibm.com> gcc/ChangeLog: * config/rs6000/rs6000.c (is_load_insn1): Verify destination is a register. (is_store_insn1): Verify source is a register. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 279f00cc648..c8a146a7d18 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -18357,8 +18357,13 @@ is_load_insn1 (rtx pat, rtx *load_mem) if (!pat || pat == NULL_RTX) return false; - if (GET_CODE (pat) == SET) - return find_mem_ref (SET_SRC (pat), load_mem); + if (GET_CODE (pat)== SET) + { + if (REG_P (SET_DEST (pat))) + return find_mem_ref (SET_SRC (pat), load_mem); + else + return false; + } if (GET_CODE (pat) == PARALLEL) { @@ -18395,7 +18400,12 @@ is_store_insn1 (rtx pat, rtx *str_mem) return false; if (GET_CODE (pat) == SET) - return find_mem_ref (SET_DEST (pat), str_mem); + { + if (REG_P (SET_SRC (pat)) || SUBREG_P (SET_SRC (pat))) + return find_mem_ref (SET_DEST (pat), str_mem); + else + return false; + } if (GET_CODE (pat) == PARALLEL) {