On Wed, Oct 13, 2021 at 10:23 AM Roger Sayle <ro...@nextmovesoftware.com> wrote:
>
>
> Good catch.  I agree with Hongtao that although my testing revealed
> no problems with the previous version of this patch, it makes sense to
> call gen_reg_rtx to generate an pseudo intermediate instead of attempting
> to reuse the existing logic that uses ix86_gen_scratch_sse_rtx as an
> intermediate.  I've left the existing behaviour the same, so that
> memory-to-memory moves (continue to) use ix86_gen_scatch_sse_rtx.
>
> This patch has been tested on x86_64-pc-linux-gnu with "make bootstrap"
> and "make -k check" with no new failures.
>
> Ok for mainline?
>
>
> 2021-10-13  Roger Sayle  <ro...@nextmovesoftware.com>
>
> gcc/ChangeLog
>         * config/i386/i386-expand.c (ix86_expand_vector_move):  Use a
>         pseudo intermediate when moving a SUBREG into a hard register,
>         by checking ix86_hardreg_mov_ok.
>         (ix86_expand_vector_extract): Store zero-extended SImode
>         intermediate in a pseudo, then set target using a SUBREG_PROMOTED
>         annotated subreg.
>         * config/i386/sse.md (mov<VMOVE>_internal): Prevent CSE creating
>         complex (SUBREG) sets of (vector) hard registers before reload, by
>         checking ix86_hardreg_mov_ok.

OK.

Thanks,
Uros.

>
> Thanks,
> Roger
>
> -----Original Message-----
> From: Hongtao Liu <crazy...@gmail.com>
> Sent: 11 October 2021 12:29
> To: Roger Sayle <ro...@nextmovesoftware.com>
> Cc: GCC Patches <gcc-patches@gcc.gnu.org>
> Subject: Re: [PATCH] x86_64: Some SUBREG related optimization tweaks to i386 
> backend.
>
> On Mon, Oct 11, 2021 at 4:55 PM Roger Sayle <ro...@nextmovesoftware.com> 
> wrote:
> > gcc/ChangeLog
> >         * config/i386/i386-expand.c (ix86_expand_vector_move):  Use a
> >         pseudo intermediate when moving a SUBREG into a hard register,
> >         by checking ix86_hardreg_mov_ok.
>
>    /* Make operand1 a register if it isn't already.  */
>    if (can_create_pseudo_p ()
> -      && !register_operand (op0, mode)
> -      && !register_operand (op1, mode))
> +      && (!ix86_hardreg_mov_ok (op0, op1)  || (!register_operand (op0,
> + mode)
> +      && !register_operand (op1, mode))))
>      {
>        rtx tmp = ix86_gen_scratch_sse_rtx (GET_MODE (op0));
>
> ix86_gen_scratch_sse_rtx probably returns a hard register, but here you want 
> a pseudo register.
>
> --
> BR,
> Hongtao
>

Reply via email to