This series provides assorted improvements for the RISC-V Zb[abcs] support collected over the last year and a half and forward-ported to the recently merged upstream support for the Zb[abcs] extensions.
Improvements include: - synthesis of HImode bswap from SImode/DImode rev8 - cost-model change to support shift-and-add (sh[123]add) in the strength-reduction of multiplication operations - support for constant-loading of (1ULL << 31) on RV64 using bseti - generating a polarity-reversed mask from a bit-test - adds orc.b as UNSPEC - improves min/minu/max/maxu patterns to suppress redundant extensions Philipp Tomsich (8): bswap: synthesize HImode bswap from SImode or DImode RISC-V: costs: handle BSWAP RISC-V: costs: support shift-and-add in strength-reduction RISC-V: bitmanip: fix constant-loading for (1ULL << 31) in DImode RISC-V: bitmanip: improvements to rotate instructions RISC-V: bitmanip: add splitter to use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" RISC-V: bitmanip: add orc.b as an unspec RISC-V: bitmanip: relax minmax to operate on GPR gcc/config/riscv/bitmanip.md | 74 +++++++++++++++++--- gcc/config/riscv/riscv.c | 31 ++++++++ gcc/config/riscv/riscv.h | 11 ++- gcc/config/riscv/riscv.md | 3 + gcc/optabs.c | 6 ++ gcc/testsuite/gcc.target/riscv/zbb-bswap.c | 22 ++++++ gcc/testsuite/gcc.target/riscv/zbb-min-max.c | 20 +++++- gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 14 ++++ 8 files changed, 162 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-bswap.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bexti.c -- 2.32.0