The current definition of vect_is_reduction (provided for target
costing) misses some pattern statements.
Regstrapped on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
Richard
gcc/
* tree-vectorizer.h (vect_is_reduction): Use STMT_VINFO_REDUC_IDX.
gcc/testsuite/
* gcc.target/aarch64/sve/cost_model_13.c: New test.
---
.../gcc.target/aarch64/sve/cost_model_13.c | 16 ++++++++++++++++
gcc/tree-vectorizer.h | 3 +--
2 files changed, 17 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cost_model_13.c
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_13.c
b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_13.c
new file mode 100644
index 00000000000..95f2ce91f80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_13.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O3 -mtune=neoverse-v1" } */
+
+int
+f11 (short *restrict x, int n)
+{
+ short res = 0;
+ for (int i = 0; i < n; ++i)
+ res += x[i];
+ return res;
+}
+
+/* We should use SVE rather than Advanced SIMD. */
+/* { dg-final { scan-assembler {\tld1h\tz[0-9]+\.h,} } } */
+/* { dg-final { scan-assembler {\tadd\tz[0-9]+\.h,} } } */
+/* { dg-final { scan-assembler-not {\tldr\tq[0-9]+,} } } */
+/* { dg-final { scan-assembler-not {\tv[0-9]+\.8h,} } } */
diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h
index 0eb13d6cc74..76e81ea546a 100644
--- a/gcc/tree-vectorizer.h
+++ b/gcc/tree-vectorizer.h
@@ -2372,8 +2372,7 @@ vect_is_store_elt_extraction (vect_cost_for_stmt kind,
stmt_vec_info stmt_info)
inline bool
vect_is_reduction (stmt_vec_info stmt_info)
{
- return (STMT_VINFO_REDUC_DEF (stmt_info)
- || VECTORIZABLE_CYCLE_DEF (STMT_VINFO_DEF_TYPE (stmt_info)));
+ return STMT_VINFO_REDUC_IDX (stmt_info) >= 0;
}
/* If STMT_INFO describes a reduction, return the vect_reduction_type
--
2.25.1
