On Tue, Mar 6, 2012 at 6:40 AM, H.J. Lu <hjl.to...@gmail.com> wrote: >>> >> >> We are expecting address to be 0x1001 - 1 == 0x1000. But, what we get >>> >> >> is 0x1000 + 0xffffffff, not 0x1000 since 0x67 address prefix only >>> >> >> applies to >>> >> >> base register to zero-extend 0xffffffff to 64bit. >>> >> > >>> >> > I would call this a bug in the specification - I guess that >>> >> > 0x1001(%eax) works correctly. >>> >> >>> >> This is how hardware works. >>> > >>> > Do you really need to use addr32 prefixes for the direct TLS seg refs? >>> > Without that the addresses will be sign-extended from the 32-bit immediate >>> > (which is used in LP64 x86_64 code too) and everything will work fine, >>> > won't >>> > it? >>> > >>> >>> 32bit immediate is OK. The problem is fs:(32bit register). >>> >> >> Just require that the MEM uses DImode address in those patterns, even for >> -mx32? >> > > Should SImode offset be zero-extended or sign-extended to > DImode? The offset relative to TP can be negative. On the > other hand, the upper 32bit address in x32 must be zero. > Even if we properly extend it to DImode, it may not be faster > than load fs:(reg) to a register first.
As I proposed earlier, just clear TARGET_TLS_DIRECT_SEG_REFS for now. This will always load fs:0 to Pmode register and will add correctly extended register or immediate to it. We can revisit this issue later to specialize for fs:reg only, but I doubt it is worth any further efforts. Uros. > > -- > H.J.