On 12/9/2021 10:32 AM, Hafiz Abid Qadeer wrote:
Commit 13b6c7639cf assumed that registers in a span will be in a certain
order. But that assumption is not true at least for the big endian targets.
Currently amdgcn is probably only target where CFA is split into multiple
registers so build_span_loc is only gets called for it. However, the
dwf_cfa_reg function where this ICE was seen can be called for any
architecture from the comparison dwf_cfa_reg (src) == cur_cfa->reg in
dwarf2out_frame_debug_expr. So dwf_cfa_reg should not assume certain
order of registers.
I was tempted to modify the assert to handle big-endian cases but that will
still be error prone and may fail on some other targets.
gcc/ChangeLog:
PR debug/103619
* dwarf2cfi.c (dwf_cfa_reg): Remove gcc_assert.
FWIW, the bogus assert can be triggered on other platforms too. c6x-elf
for example with -mbig-endian.
I don't know enough about this code to review.
jeff
