Arm 32, x86 (32) and mips has support for Asan[1], so we can `reference` how they implement that, but I guess the problem is we need someone to do that.
[1] https://github.com/llvm/llvm-project/blob/main/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake#L28 On Thu, Apr 21, 2022 at 7:54 AM Palmer Dabbelt <pal...@dabbelt.com> wrote: > > On Tue, 19 Apr 2022 23:13:15 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > > Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is > > still unsupported for RISC-V. If I add '--enable-libsanitizer' in > > Makefile.in to reconfigure, there are compiling errors. > > Is it because # libsanitizer not supported rv32, but it will break the rv64 > > multi-lib build, so we disable that temporally until rv32 supported# in > > Makefile.in? > > Not quite sure what's going on here, I keep getting copies of this > message that look empty in gmail. > > I was under the impression that asan worked on rv64, but remember there > being some worrisome constants floating around (as Jim alludes to in the > forwarded patch). As far as I can tell there's no libsanitizer support > for rv32 (upstream is at LLVM), probably because we didn't have a stable > uABI back then. It's not super hard to do a libsanitizer port, but I > don't see any other 32-bit targets with asan so either I'm missing > something or it's tricky (and we don't have much free VA space, so not > sure if it'd even run anything useful). > > > ------------------------------------------------------------------ > > 发件人：Jim Wilson <j...@sifive.com> > > 发送时间：2020年10月29日(星期四) 07:59 > > 收件人：gcc-patches <gcc-patches@gcc.gnu.org> > > 抄 送：cooper.joshua <cooper.jos...@linux.alibaba.com>; Jim Wilson > > <j...@sifive.com> > > 主 题：[PATCH] Asan changes for RISC-V. > > > > We have only riscv64 asan support, there is no riscv32 support as yet. So I > > need to be able to conditionally enable asan support for the riscv target. > > I > > implemented this by returning zero from the asan_shadow_offset function. > > This > > requires a change to toplev.c and docs in target.def. > > > > The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel. > > The problem is that the asan high memory region is a small wedge below > > 0x4000000000. The new kernel puts shared libraries at 0x3fffffffff and > > going > > down which works. But the old kernel puts shared libraries at 0x2000000000 > > and going up which does not work, as it isn't in any recognized memory > > region. This might be fixable with more asan work, but we don't really need > > support for old kernel versions. > > > > The asan port is curious in that it uses 1<<29 for the shadow offset, but > > all > > other 64-bit targets use a number larger than 1<<32. But what we have is > > working OK for now. > > > > I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running > > on > > qemu and the results look reasonable. > > > > === gcc Summary === > > > > # of expected passes 1905 > > # of unexpected failures 11 > > # of unsupported tests 224 > > > > === g++ Summary === > > > > # of expected passes 2002 > > # of unexpected failures 6 > > # of unresolved testcases 1 > > # of unsupported tests 175 > > > > OK? > > > > Jim > > > > 2020-10-28 Jim Wilson <j...@sifive.com> > > > > gcc/ > > * config/riscv/riscv.c (riscv_asan_shadow_offset): New. > > (TARGET_ASAN_SHADOW_OFFSET): New. > > * doc/tm.texi: Regenerated. > > * target.def (asan_shadow_offset); Mention that it can return zero. > > * toplev.c (process_options): Check for and handle zero return from > > targetm.asan_shadow_offset call. > > > > Co-Authored-By: cooper.joshua <cooper.jos...@linux.alibaba.com> > > --- > > gcc/config/riscv/riscv.c | 16 ++++++++++++++++ > > gcc/doc/tm.texi | 3 ++- > > gcc/target.def | 3 ++- > > gcc/toplev.c | 3 ++- > > 4 files changed, 22 insertions(+), 3 deletions(-) > > > > diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c > > index 989a9f15250..6909e200de1 100644 > > --- a/gcc/config/riscv/riscv.c > > +++ b/gcc/config/riscv/riscv.c > > @@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op) > > return true; > > } > > > > +/* Implement TARGET_ASAN_SHADOW_OFFSET. */ > > + > > +static unsigned HOST_WIDE_INT > > +riscv_asan_shadow_offset (void) > > +{ > > + /* We only have libsanitizer support for RV64 at present. > > + > > + This number must match kRiscv*_ShadowOffset* in the file > > + libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64, > > + even though 1<<36 makes more sense. */ > > + return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0; > > +} > > + > > /* Initialize the GCC target structure. */ > > #undef TARGET_ASM_ALIGNED_HI_OP > > #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" > > @@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op) > > #undef TARGET_NEW_ADDRESS_PROFITABLE_P > > #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p > > > > +#undef TARGET_ASAN_SHADOW_OFFSET > > +#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset > > + > > struct gcc_target targetm = TARGET_INITIALIZER; > > > > #include "gt-riscv.h" > > diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi > > index 24c37f655c8..39c596b647a 100644 > > --- a/gcc/doc/tm.texi > > +++ b/gcc/doc/tm.texi > > @@ -12078,7 +12078,8 @@ is zero, which disables this optimization. > > @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} > > TARGET_ASAN_SHADOW_OFFSET (void) > > Return the offset bitwise ored into shifted address to get corresponding > > Address Sanitizer shadow memory address. NULL if Address Sanitizer is not > > -supported by the target. > > +supported by the target. May return 0 if Address Sanitizer is not > > supported > > +by a subtarget. > > @end deftypefn > > > > @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK > > (unsigned HOST_WIDE_INT @var{val}) > > diff --git a/gcc/target.def b/gcc/target.def > > index ed2da154e30..268b56b6ebd 100644 > > --- a/gcc/target.def > > +++ b/gcc/target.def > > @@ -4452,7 +4452,8 @@ DEFHOOK > > (asan_shadow_offset, > > "Return the offset bitwise ored into shifted address to get > > corresponding\n\ > > Address Sanitizer shadow memory address. NULL if Address Sanitizer is > > not\n\ > > -supported by the target.", > > +supported by the target. May return 0 if Address Sanitizer is not > > supported\n\ > > +by a subtarget.", > > unsigned HOST_WIDE_INT, (void), > > NULL) > > > > diff --git a/gcc/toplev.c b/gcc/toplev.c > > index 20e231f4d2a..cf89598252c 100644 > > --- a/gcc/toplev.c > > +++ b/gcc/toplev.c > > @@ -1834,7 +1834,8 @@ process_options (void) > > } > > > > if ((flag_sanitize & SANITIZE_USER_ADDRESS) > > - && targetm.asan_shadow_offset == NULL) > > + && ((targetm.asan_shadow_offset == NULL) > > + || (targetm.asan_shadow_offset () == 0))) > > { > > warning_at (UNKNOWN_LOCATION, 0, > > "%<-fsanitize=address%> not supported for this target"); > > -- > > 2.17.1
