From: Jia-Wei Chen <jia...@iscas.ac.cn> Support 'TARGET_ZFINX' with float instruction pattern and builtin function. Reuse 'TARGET_HADR_FLOAT' and 'TARGET_DOUBLE_FLOAT' patterns.
gcc/ChangeLog: * config/riscv/riscv-builtins.cc (AVAIL): Add TARGET_ZFINX. (riscv_atomic_assign_expand_fenv): Ditto. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add TARGET_ZFINX. * config/riscv/riscv.md (TARGET_HARD_FLOAT): Add TARGET_ZFINX. (TARGET_HARD_FLOAT || TARGET_ZFINX): Add TARGET_ZFINX. (TARGET_DOUBLE_FLOAT || TARGET_ZDINX): Add TARGET_ZDINX. Co-Authored-By: Sinan Lin. --- gcc/config/riscv/riscv-builtins.cc | 4 +- gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv.md | 76 +++++++++++++++--------------- 3 files changed, 41 insertions(+), 41 deletions(-) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 0658f8d3047..21896d747f5 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -85,7 +85,7 @@ struct riscv_builtin_description { unsigned int (*avail) (void); }; -AVAIL (hard_float, TARGET_HARD_FLOAT) +AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX) /* Construct a riscv_builtin_description from the given arguments. @@ -279,7 +279,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, void riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) { - if (!TARGET_HARD_FLOAT) + if (!(TARGET_HARD_FLOAT || TARGET_ZFINX)) return; tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags); diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index eb7ef09297e..a9c43a64fd4 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -58,7 +58,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) if (TARGET_HARD_FLOAT) builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8); - if (TARGET_HARD_FLOAT && TARGET_FDIV) + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) { builtin_define ("__riscv_fdiv"); builtin_define ("__riscv_fsqrt"); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d9b451be0b4..f81e315666e 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -300,8 +300,8 @@ (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")]) ;; Iterator for hardware-supported floating-point modes. -(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") - (DF "TARGET_DOUBLE_FLOAT")]) +(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX") + (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")]) ;; Iterator for floating-point modes that can be loaded into X registers. (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")]) @@ -448,7 +448,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (plus:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fadd.<fmt>\t%0,%1,%2" [(set_attr "type" "fadd") (set_attr "mode" "<UNITMODE>")]) @@ -579,7 +579,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (minus:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsub.<fmt>\t%0,%1,%2" [(set_attr "type" "fadd") (set_attr "mode" "<UNITMODE>")]) @@ -749,7 +749,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (mult:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmul.<fmt>\t%0,%1,%2" [(set_attr "type" "fmul") (set_attr "mode" "<UNITMODE>")]) @@ -1056,7 +1056,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (div:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT && TARGET_FDIV" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" "fdiv.<fmt>\t%0,%1,%2" [(set_attr "type" "fdiv") (set_attr "mode" "<UNITMODE>")]) @@ -1071,7 +1071,7 @@ (define_insn "sqrt<mode>2" [(set (match_operand:ANYF 0 "register_operand" "=f") (sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT && TARGET_FDIV" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" { return "fsqrt.<fmt>\t%0,%1"; } @@ -1086,7 +1086,7 @@ (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmadd.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1097,7 +1097,7 @@ (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmsub.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1109,7 +1109,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fnmadd.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1121,7 +1121,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fnmsub.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1134,7 +1134,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" "fmadd.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1147,7 +1147,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" "fmsub.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1160,7 +1160,7 @@ (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" "fnmadd.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1173,7 +1173,7 @@ (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (<MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (<MODE>mode)" "fnmsub.<fmt>\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "<UNITMODE>")]) @@ -1188,7 +1188,7 @@ (define_insn "abs<mode>2" [(set (match_operand:ANYF 0 "register_operand" "=f") (abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fabs.<fmt>\t%0,%1" [(set_attr "type" "fmove") (set_attr "mode" "<UNITMODE>")]) @@ -1198,7 +1198,7 @@ (unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")] UNSPEC_COPYSIGN))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsgnj.<fmt>\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "<UNITMODE>")]) @@ -1206,7 +1206,7 @@ (define_insn "neg<mode>2" [(set (match_operand:ANYF 0 "register_operand" "=f") (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fneg.<fmt>\t%0,%1" [(set_attr "type" "fmove") (set_attr "mode" "<UNITMODE>")]) @@ -1223,7 +1223,7 @@ (unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f")) (use (match_operand:ANYF 2 "register_operand" " f"))] UNSPEC_FMIN))] - "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)" "fmin.<fmt>\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "<UNITMODE>")]) @@ -1233,7 +1233,7 @@ (unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f")) (use (match_operand:ANYF 2 "register_operand" " f"))] UNSPEC_FMAX))] - "TARGET_HARD_FLOAT && !HONOR_SNANS (<MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (<MODE>mode)" "fmax.<fmt>\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "<UNITMODE>")]) @@ -1242,7 +1242,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (smin:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmin.<fmt>\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "<UNITMODE>")]) @@ -1251,7 +1251,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (smax:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmax.<fmt>\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "<UNITMODE>")]) @@ -1312,7 +1312,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "register_operand" " f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" "fcvt.s.d\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF")]) @@ -1438,7 +1438,7 @@ [(set (match_operand:DF 0 "register_operand" "=f") (float_extend:DF (match_operand:SF 1 "register_operand" " f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" "fcvt.d.s\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "DF")]) @@ -1454,7 +1454,7 @@ [(set (match_operand:GPR 0 "register_operand" "=r") (fix:GPR (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,rtz" [(set_attr "type" "fcvt") (set_attr "mode" "<ANYF:MODE>")]) @@ -1463,7 +1463,7 @@ [(set (match_operand:GPR 0 "register_operand" "=r") (unsigned_fix:GPR (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.<GPR:ifmt>u.<ANYF:fmt> %0,%1,rtz" [(set_attr "type" "fcvt") (set_attr "mode" "<ANYF:MODE>")]) @@ -1472,7 +1472,7 @@ [(set (match_operand:ANYF 0 "register_operand" "= f") (float:ANYF (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.<ANYF:fmt>.<GPR:ifmt>\t%0,%z1" [(set_attr "type" "fcvt") (set_attr "mode" "<ANYF:MODE>")]) @@ -1481,7 +1481,7 @@ [(set (match_operand:ANYF 0 "register_operand" "= f") (unsigned_float:ANYF (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.<ANYF:fmt>.<GPR:ifmt>u\t%0,%z1" [(set_attr "type" "fcvt") (set_attr "mode" "<ANYF:MODE>")]) @@ -1491,7 +1491,7 @@ (unspec:GPR [(match_operand:ANYF 1 "register_operand" " f")] RINT))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>" [(set_attr "type" "fcvt") (set_attr "mode" "<ANYF:MODE>")]) @@ -1765,7 +1765,7 @@ (define_insn "*movdf_hardfloat_rv32" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m, *r,*r,*m") (match_operand:DF 1 "move_operand" " f,G,m,f,G,*r*G,*m,*r"))] - "!TARGET_64BIT && TARGET_DOUBLE_FLOAT + "!TARGET_64BIT && (TARGET_DOUBLE_FLOAT || TARGET_ZDINX) && (register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } @@ -2214,7 +2214,7 @@ (match_operand:ANYF 2 "register_operand")]) (label_ref (match_operand 3 "")) (pc)))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" { riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]), operands[1], operands[2]); @@ -2303,7 +2303,7 @@ (match_operator:SI 1 "fp_scc_comparison" [(match_operand:ANYF 2 "register_operand") (match_operand:ANYF 3 "register_operand")]))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" { riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2], operands[3]); @@ -2315,7 +2315,7 @@ (match_operator:X 1 "fp_native_comparison" [(match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")]))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "f%C1.<fmt>\t%0,%2,%3" [(set_attr "type" "fcmp") (set_attr "mode" "<UNITMODE>")]) @@ -2327,7 +2327,7 @@ (match_operand:ANYF 2 "register_operand")] QUIET_COMPARISON)) (clobber (match_scratch:X 3))])] - "TARGET_HARD_FLOAT") + "TARGET_HARD_FLOAT || TARGET_ZFINX") (define_insn "*f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_default" [(set (match_operand:X 0 "register_operand" "=r") @@ -2336,7 +2336,7 @@ (match_operand:ANYF 2 "register_operand" " f")] QUIET_COMPARISON)) (clobber (match_scratch:X 3 "=&r"))] - "TARGET_HARD_FLOAT && ! HONOR_SNANS (<ANYF:MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && ! HONOR_SNANS (<ANYF:MODE>mode)" "frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3" [(set_attr "type" "fcmp") (set_attr "mode" "<UNITMODE>") @@ -2349,7 +2349,7 @@ (match_operand:ANYF 2 "register_operand" " f")] QUIET_COMPARISON)) (clobber (match_scratch:X 3 "=&r"))] - "TARGET_HARD_FLOAT && HONOR_SNANS (<ANYF:MODE>mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && HONOR_SNANS (<ANYF:MODE>mode)" "frflags\t%3\n\tf<quiet_pattern>.<fmt>\t%0,%1,%2\n\tfsflags %3\n\tfeq.<fmt>\tzero,%1,%2" [(set_attr "type" "fcmp") (set_attr "mode" "<UNITMODE>") @@ -2753,12 +2753,12 @@ (define_insn "riscv_frflags" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "frflags\t%0") (define_insn "riscv_fsflags" [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsflags\t%0") (define_insn "riscv_mret" -- 2.25.1