Hi, Segher
On 8/7/2022 上午 1:31, Segher Boessenkool wrote:
>> --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c
>> @@ -2,14 +2,14 @@
>> /* { dg-options "-O2" } */
>>
>> /* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 14121 { target ilp32 }
>> } } */
>> -/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 20217 { target lp64 }
>> } } */
>> +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 21279 { target lp64 }
>> } } */
> You are saying there should be 21279 instructions generated by this test
> case. What makes you say that? Yes, we regressed some time ago, we
> generate too many insns in many cases, but that is *bad*.
>
The trunk generates 21305. My patch generates 26 "rlwimi" instead of
"rlwimn+ior". So
it saves 26 insns and reduce the total number of insns from 21305 to 21279 and
increase the number of "rlwimi" from 1666 to 1692.
I did a biset for the problem. After commit "commit 8d2d39587: combine: Do not
combine
moves from hard registers", the case fails. The root cause is it can't combine
from the
hard registers and has to use subreg which causes its high part to be
undefined. Thus,
there is an additional "AND" generated.
Before the commit
Trying 2 -> 7:
2: r125:DI=%3:DI
REG_DEAD %3:DI
7: r128:SI=r125:DI#0 0>>0x1f
REG_DEAD r125:DI
Successfully matched this instruction:
(set (reg:SI 128 [ x ])
(lshiftrt:SI (reg:SI 3 3 [ x ])
(const_int 31 [0x1f])))
allowing combination of insns 2 and 7
After the commit
Trying 20 -> 7:
20: r125:DI=r132:DI
REG_DEAD r132:DI
7: r128:SI=r125:DI#0 0>>0x1f
REG_DEAD r125:DI
Failed to match this instruction:
(set (subreg:DI (reg:SI 128 [ x ]) 0)
(zero_extract:DI (reg:DI 132)
(const_int 32 [0x20])
(const_int 1 [0x1])))
Successfully matched this instruction:
(set (subreg:DI (reg:SI 128 [ x ]) 0)
(and:DI (lshiftrt:DI (reg:DI 132)
(const_int 31 [0x1f]))
(const_int 4294967295 [0xffffffff])))
allowing combination of insns 20 and 7
The problem should be fixed in another case? Please advice.
Thanks
Gui Haochen
