From: Andrew Pinski <apin...@marvell.com>
The default expansion for bswap16 is two extractions (shift/and)
followed by an insertation (ior) and then a zero extend. This can be improved
with ZBB enabled to just full byteswap followed by a (logical) shift right.
This patch adds a new pattern for this which does that.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu.
gcc/ChangeLog:
PR target/106601
* config/riscv/bitmanip.md (bswaphi2): New pattern.
gcc/testsuite/ChangeLog:
PR target/106601
* gcc.target/riscv/zbb_32_bswap-2.c: New test.
* gcc.target/riscv/zbb_bswap-2.c: New test.
Change-Id: If61362c14664cf8685da17779217033689878f86
---
gcc/config/riscv/bitmanip.md | 24 +++++++++++++++++++
.../gcc.target/riscv/zbb_32_bswap-2.c | 12 ++++++++++
gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c | 12 ++++++++++
3 files changed, 48 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index c7ba667f87a..c4383285d81 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -276,6 +276,30 @@ (define_insn "bswap<mode>2"
"rev8\t%0,%1"
[(set_attr "type" "bitmanip")])
+;; HI bswap can be emulated using SI/DI bswap followed
+;; by a logical shift right
+;; SI bswap for TARGET_64BIT is already similarly in
+;; the common code.
+(define_expand "bswaphi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
+ "TARGET_ZBB"
+{
+ rtx tmp = gen_reg_rtx (word_mode);
+ rtx newop1 = gen_lowpart (word_mode, operands[1]);
+ if (TARGET_64BIT)
+ emit_insn (gen_bswapdi2 (tmp, newop1));
+ else
+ emit_insn (gen_bswapsi2 (tmp, newop1));
+ rtx tmp1 = gen_reg_rtx (word_mode);
+ if (TARGET_64BIT)
+ emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16)));
+ else
+ emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16)));
+ emit_move_insn (operands[0], gen_lowpart (HImode, tmp1));
+ DONE;
+})
+
(define_insn "<bitmanip_optab><mode>3"
[(set (match_operand:X 0 "register_operand" "=r")
(bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
new file mode 100644
index 00000000000..679b34c4e41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+ return __builtin_bswap16(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+/* { dg-final { scan-assembler "srli" } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
new file mode 100644
index 00000000000..c358f6683f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+int foo(int n)
+{
+ return __builtin_bswap16(n);
+}
+
+/* { dg-final { scan-assembler "rev8" } } */
+/* { dg-final { scan-assembler "srli" } } */
+
--
2.17.1
