xtensa may use up to 4 registers to return a value from a function, but recognition of only one register in the xtensa_function_value_regno_p and missing untyped_call pattern result in that only one register is saved by the __builtin_apply and returned by the __builtin_apply_return.
gcc/ * config/xtensa/xtensa.cc (xtensa_function_value_regno_p): Recognize all 4 return registers. * config/xtensa/xtensa.h (GP_RETURN_REG_COUNT): New definition. * config/xtensa/xtensa.md (untyped_call): New pattern. --- gcc/config/xtensa/xtensa.cc | 2 +- gcc/config/xtensa/xtensa.h | 1 + gcc/config/xtensa/xtensa.md | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index ac52c015a94c..f1b3331ea558 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -4472,7 +4472,7 @@ xtensa_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) static bool xtensa_function_value_regno_p (const unsigned int regno) { - return (regno == GP_RETURN); + return (regno >= GP_RETURN && regno < GP_RETURN + GP_RETURN_REG_COUNT); } /* The static chain is passed in memory. Provide rtx giving 'mem' diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 0f3006d7af8f..16e3d55e8963 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -488,6 +488,7 @@ enum reg_class point, and values of coprocessor and user-defined modes. */ #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) +#define GP_RETURN_REG_COUNT 4 /* Symbolic macros for the first/last argument registers. */ #define GP_ARG_FIRST (GP_REG_FIRST + 2) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index f722ea562891..608110c20bcb 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -2305,6 +2305,27 @@ (set_attr "mode" "none") (set_attr "length" "3")]) +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "") + (const_int 0)) + (match_operand 1 "") + (match_operand 2 "")])] + "" +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + emit_insn (gen_blockage ()); + DONE; +}) + (define_insn "entry" [(set (reg:SI A1_REG) (unspec_volatile:SI [(match_operand:SI 0 "const_int_operand" "i")] -- 2.30.2