On 10/11/22 13:31, Palmer Dabbelt wrote:
On Tue, 11 Oct 2022 12:06:27 PDT (-0700), Vineet Gupta wrote:
Hi Christoph, Kito,
On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote:
This series provides a cleanup of the current atomics implementation
of RISC-V:
* PR100265: Use proper fences for atomic load/store
* PR100266: Provide programmatic implementation of CAS
As both are very related, I merged the patches into one series.
The first patch could be squashed into the following patches,
but I found it easier to understand the chances with it in place.
The series has been tested as follows:
* Building and testing a multilib RV32/64 toolchain
(bootstrapped with riscv-gnu-toolchain repo)
* Manual review of generated sequences for GCC's atomic builtins API
The programmatic re-implementation of CAS benefits from a REE
improvement
(see PR100264):
https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568680.html
If this patch is not in place, then an additional extension instruction
is emitted after the SC.W (in case of RV64 and CAS for uint32_t).
Further, the new CAS code requires cbranch INSN helpers to be present:
https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569689.html
I was wondering is this patchset is blocked on some technical grounds.
There's a v3 (though I can't find all of it, so not quite sure what
happened), but IIUC that still has the same fundamental problems that
all these have had: changing over to the new fence model may by an ABI
break and the split CAS implementation doesn't ensure eventual success
(see Jim's comments). Not sure if there's other comments floating
around, though, that's just what I remember.
Do we have a pointer to the ABI discussion. I've been meaning to
familiarize myself with the issues in this space and that seems like a
good place to start given its blocking progress on the atomics.
jeff
