The RV32A extension does not support 64-bit atomic operations. For RTEMS, use a 32-bit gcov type for RV32.
gcc/ChangeLog: * config/riscv/riscv.cc (riscv_gcov_type_size): New. (TARGET_GCOV_TYPE_SIZE): Likewise. * config/riscv/rtems.h (RISCV_GCOV_TYPE_SIZE): New. --- gcc/config/riscv/riscv.cc | 11 +++++++++++ gcc/config/riscv/rtems.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4e18a43539a..1b7f4fb1981 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6637,6 +6637,17 @@ riscv_vector_alignment (const_tree type) #undef TARGET_VECTOR_ALIGNMENT #define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment +#ifdef RISCV_GCOV_TYPE_SIZE +static HOST_WIDE_INT +riscv_gcov_type_size (void) +{ + return RISCV_GCOV_TYPE_SIZE; +} + +#undef TARGET_GCOV_TYPE_SIZE +#define TARGET_GCOV_TYPE_SIZE riscv_gcov_type_size +#endif + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/rtems.h b/gcc/config/riscv/rtems.h index 14e5e59caaa..3982b24382f 100644 --- a/gcc/config/riscv/rtems.h +++ b/gcc/config/riscv/rtems.h @@ -29,3 +29,5 @@ builtin_define ("__USE_INIT_FINI__"); \ builtin_assert ("system=rtems"); \ } while (0) + +#define RISCV_GCOV_TYPE_SIZE (TARGET_64BIT ? 64 : 32) -- 2.35.3