verified and committed
On Tue, Oct 25, 2022 at 2:18 PM Monk Chiang <monk.chi...@sifive.com> wrote:
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_ext_version_table):
> Add svinval and svnapot extension.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_SVINVAL): New.
> (MASK_SVNAPOT): Ditto.
> (TARGET_SVINVAL): Ditto.
> (TARGET_SVNAPOT): Ditto.
> * config/riscv/riscv.opt (riscv_sv_subext): New.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/predef-23.c:New.
> * gcc.target/riscv/predef-24.c:Ditto.
> ---
> gcc/common/config/riscv/riscv-common.cc | 6 +++
> gcc/config/riscv/riscv-opts.h | 6 +++
> gcc/config/riscv/riscv.opt | 3 ++
> gcc/testsuite/gcc.target/riscv/predef-23.c | 47 ++++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/predef-24.c | 47 ++++++++++++++++++++++
> 5 files changed, 109 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-23.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/predef-24.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index dead3802f83..a5fe782bb61 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -202,6 +202,9 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
>
> {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> + {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
> +
> /* Terminate the list. */
> {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> };
> @@ -1226,6 +1229,9 @@ static const riscv_ext_flag_table_t
> riscv_ext_flag_table[] =
>
> {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> + {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
> + {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
> +
> {NULL, NULL, 0}
> };
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 55e0bc0a0e9..63ac56a8ca0 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -162,6 +162,12 @@ enum stack_protector_guard {
> #define MASK_ZMMUL (1 << 0)
> #define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
>
> +#define MASK_SVINVAL (1 << 0)
> +#define MASK_SVNAPOT (1 << 1)
> +
> +#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
> +#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
> +
> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
> popcount to caclulate the minimal VLEN. */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 8923a11a97d..949311775c1 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -224,6 +224,9 @@ int riscv_zf_subext
> TargetVariable
> int riscv_zm_subext
>
> +TargetVariable
> +int riscv_sv_subext
> +
> Enum
> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> Supported ISA specs (for use with the -misa-spec= option):
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-23.c
> b/gcc/testsuite/gcc.target/riscv/predef-23.c
> new file mode 100644
> index 00000000000..64bde17efa9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-23.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_svinval -mabi=lp64 -mcmodel=medlow
> -misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_c) || (__riscv_c != (2 * 1000 * 1000))
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_e)
> +#error "__riscv_e"
> +#endif
> +
> +#if !defined(__riscv_a) || (__riscv_a != (2 * 1000 * 1000 + 1 * 1000))
> +#error "__riscv_a"
> +#endif
> +
> +#if !defined(__riscv_m) || (__riscv_m != (2 * 1000 * 1000))
> +#error "__riscv_m"
> +#endif
> +
> +#if !defined(__riscv_f) || (__riscv_f != (2 * 1000 * 1000 + 2 * 1000))
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_d) || (__riscv_d != (2 * 1000 * 1000 + 2 * 1000))
> +#error "__riscv_d"
> +#endif
> +
> +#if !defined(__riscv_svinval)
> +#error "__riscv_svinval"
> +#endif
> +
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-24.c
> b/gcc/testsuite/gcc.target/riscv/predef-24.c
> new file mode 100644
> index 00000000000..2b51a19eacd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-24.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_svnapot -mabi=lp64 -mcmodel=medlow
> -misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_c) || (__riscv_c != (2 * 1000 * 1000))
> +#error "__riscv_c"
> +#endif
> +
> +#if defined(__riscv_e)
> +#error "__riscv_e"
> +#endif
> +
> +#if !defined(__riscv_a) || (__riscv_a != (2 * 1000 * 1000 + 1 * 1000))
> +#error "__riscv_a"
> +#endif
> +
> +#if !defined(__riscv_m) || (__riscv_m != (2 * 1000 * 1000))
> +#error "__riscv_m"
> +#endif
> +
> +#if !defined(__riscv_f) || (__riscv_f != (2 * 1000 * 1000 + 2 * 1000))
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_d) || (__riscv_d != (2 * 1000 * 1000 + 2 * 1000))
> +#error "__riscv_d"
> +#endif
> +
> +#if !defined(__riscv_svnapot)
> +#error "__riscv_svnapot"
> +#endif
> +
> + return 0;
> +}
> --
> 2.37.2
>
