Both the XVentanaCondOps (a vendor-defined extension from Ventana Microsystems) and the proposed ZiCondOps extensions define a conditional-zero(-or-value) instruction, which is similar to the following C construct: rd = rc ? rs : 0
This functionality can be tied back into if-convertsion and also match some typical programming idioms. This series includes backend support for XVentanaCondops and infrastructure to handle conditional-zero constructions in if-conversion. Tested against SPEC CPU 2017. Philipp Tomsich (7): RISC-V: Recognize xventanacondops extension RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Recognize bexti in negated if-conversion RISC-V: Support immediates in XVentanaCondOps ifcvt: add if-conversion to conditional-zero instructions gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/predicates.md | 12 + gcc/config/riscv/riscv-opts.h | 3 + gcc/config/riscv/riscv.cc | 14 ++ gcc/config/riscv/riscv.md | 27 +++ gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/xventanacondops.md | 150 ++++++++++++ gcc/ifcvt.cc | 214 ++++++++++++++++++ .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ .../riscv/xventanacondops-ifconv-imm.c | 19 ++ .../gcc.target/riscv/xventanacondops-le-01.c | 17 ++ .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-lt-03.c | 17 ++ .../gcc.target/riscv/xventanacondops-ne-01.c | 11 + .../gcc.target/riscv/xventanacondops-ne-03.c | 15 ++ .../gcc.target/riscv/xventanacondops-ne-04.c | 15 ++ .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ 20 files changed, 605 insertions(+) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c -- 2.34.1