From: Christoph Müllner <christoph.muell...@vrull.eu>
This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding mov<mode>cc accordingly and adjust the cost
model.
gcc/ChangeLog:
* config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
XTheadCondMov.
(riscv_expand_conditional_move_onesided): New function.
(riscv_expand_conditional_move): New function.
* config/riscv/riscv.md: Add support for XTheadCondMov.
* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add
support for XTheadCondMov.
(*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test.
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
---
gcc/config/riscv/iterators.md | 4 ++
gcc/config/riscv/riscv.cc | 53 ++++++++++++++++---
gcc/config/riscv/riscv.md | 7 +--
gcc/config/riscv/thead.md | 35 ++++++++++++
.../riscv/xtheadcondmov-mveqz-imm-eqz.c | 37 +++++++++++++
.../riscv/xtheadcondmov-mveqz-imm-not.c | 37 +++++++++++++
.../riscv/xtheadcondmov-mveqz-reg-eqz.c | 37 +++++++++++++
.../riscv/xtheadcondmov-mveqz-reg-not.c | 37 +++++++++++++
.../riscv/xtheadcondmov-mvnez-imm-cond.c | 37 +++++++++++++
.../riscv/xtheadcondmov-mvnez-imm-nez.c | 37 +++++++++++++
.../riscv/xtheadcondmov-mvnez-reg-cond.c | 37 +++++++++++++
.../riscv/xtheadcondmov-mvnez-reg-nez.c | 37 +++++++++++++
12 files changed, 386 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
create mode 100644
gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
create mode 100644
gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 50380ecfac9..3932eab14fa 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -26,6 +26,10 @@
;; from the same template.
(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
+;; A copy of GPR that can be used when a pattern has two independent
+;; modes.
+(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
+
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index decade0fedd..9a795264e00 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2269,8 +2269,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBUTE_UN
return false;
case IF_THEN_ELSE:
- if (TARGET_SFB_ALU
- && register_operand (XEXP (x, 1), mode)
+ if ((TARGET_SFB_ALU || TARGET_XTHEADCONDMOV)
+ && reg_or_0_operand (XEXP (x, 1), mode)
&& sfb_alu_operand (XEXP (x, 2), mode)
&& comparison_operator (XEXP (x, 0), VOIDmode))
{
@@ -3231,16 +3231,57 @@ riscv_expand_conditional_branch (rtx label, rtx_code
code, rtx op0, rtx op1)
emit_jump_insn (gen_condjump (condition, label));
}
+/* Helper to emit two one-sided conditional moves for the movecc. */
+
+static void
+riscv_expand_conditional_move_onesided (rtx dest, rtx cons, rtx alt,
+ rtx_code code, rtx op0, rtx op1)
+{
+ machine_mode mode = GET_MODE (dest);
+
+ gcc_assert (GET_MODE_CLASS (mode) == MODE_INT);
+ gcc_assert (reg_or_0_operand (cons, mode));
+ gcc_assert (reg_or_0_operand (alt, mode));
+
+ riscv_emit_int_compare (&code, &op0, &op1);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+
+ rtx tmp1 = gen_reg_rtx (mode);
+ rtx tmp2 = gen_reg_rtx (mode);
+
+ emit_insn (gen_rtx_SET (tmp1, gen_rtx_IF_THEN_ELSE (mode, cond,
+ cons, const0_rtx)));
+
+ /* We need to expand a sequence for both blocks and we do that such,
+ that the second conditional move will use the inverted condition.
+ We use temporaries that are or'd to the dest register. */
+ cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, GET_MODE (op0), op0, op1);
+ emit_insn (gen_rtx_SET (tmp2, gen_rtx_IF_THEN_ELSE (mode, cond,
+ alt, const0_rtx)));
+
+ emit_insn (gen_rtx_SET (dest, gen_rtx_IOR (mode, tmp1, tmp2)));
+ }
+
/* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
void
riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code,
rtx op0, rtx op1)
{
- riscv_emit_int_compare (&code, &op0, &op1);
- rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
- emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond,
- cons, alt)));
+ machine_mode mode = GET_MODE (dest);
+
+ if (TARGET_XTHEADCONDMOV
+ && GET_MODE_CLASS (mode) == MODE_INT
+ && reg_or_0_operand (cons, mode)
+ && reg_or_0_operand (alt, mode))
+ riscv_expand_conditional_move_onesided (dest, cons, alt, code, op0, op1);
+ else
+ {
+ riscv_emit_int_compare (&code, &op0, &op1);
+ rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+ emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest),
+ cond, cons, alt)));
+ }
}
/* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a9254df7820..850a2d958e4 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -233,6 +233,7 @@ (define_attr "enabled" "no,yes"
;; nop no operation
;; ghost an instruction that produces no real code
;; bitmanip bit manipulation instructions
+;; condmove conditional moves
;; Classification of RVV instructions which will be added to each RVV .md
pattern and used by scheduler.
;; rdvlenb vector byte length vlenb csrr read
;; rdvl vector length vl csrr read
@@ -324,7 +325,7 @@ (define_attr "type"
"unknown,branch,jump,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
- atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
+ atomic,condmove,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
@@ -2223,9 +2224,9 @@ (define_insn "*branch<mode>"
(define_expand "mov<mode>cc"
[(set (match_operand:GPR 0 "register_operand")
(if_then_else:GPR (match_operand 1 "comparison_operator")
- (match_operand:GPR 2 "register_operand")
+ (match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "sfb_alu_operand")))]
- "TARGET_SFB_ALU"
+ "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV"
{
rtx cmp = operands[1];
/* We only handle word mode integer compares for now. */
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 676d10b71d7..e9a6c1eeb71 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -36,3 +36,38 @@ (define_insn "*th_tst"
"TARGET_XTHEADBS"
"th.tst\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+
+(define_insn "*th_cond_mov<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ (if_then_else:GPR
+ (match_operator 4 "equality_operator"
+ [(match_operand:GPR2 1 "register_operand" "r,r")
+ (const_int 0)])
+ (match_operand:GPR 2 "reg_or_0_operand" "rJ,0")
+ (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))]
+ "TARGET_XTHEADCONDMOV"
+{
+ if (which_alternative == 0)
+ return "th.mv%C4z\t%0,%z2,%1";
+
+ /* Invert the condition and take else-block. */
+ rtx_code code = GET_CODE (operands[4]);
+ code = (code == EQ) ? NE : EQ;
+ operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx);
+ return "th.mv%C4z\t%0,%z3,%1";
+}
+ [(set_attr "type" "condmove")
+ (set_attr "mode" "<GPR:MODE>")])
+
+(define_insn "*th_cond_gpr_mov<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r")
+ (if_then_else:GPR
+ (match_operand:GPR2 1 "register_operand" "r,r")
+ (match_operand:GPR 2 "reg_or_0_operand" "rJ,0")
+ (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))]
+ "TARGET_XTHEADCONDMOV"
+ "@
+ th.mvnez\t%0,%z2,%1
+ th.mveqz\t%0,%z3,%1"
+ [(set_attr "type" "condmove")
+ (set_attr "mode" "<GPR:MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
new file mode 100644
index 00000000000..c66ec7fadbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (cond == 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (cond == 0)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (cond == 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (cond == 0)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
new file mode 100644
index 00000000000..c076dbca4ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (!cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (!cond)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (!cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (!cond)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
new file mode 100644
index 00000000000..3e2e369bdb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (cond == 0)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
new file mode 100644
index 00000000000..c387d1c5f98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (!cond)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
new file mode 100644
index 00000000000..95b396057da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (cond)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (cond)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (cond)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
new file mode 100644
index 00000000000..cc17f1bd82d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond)
+{
+ if (cond != 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_int (long x, int cond)
+{
+ if (cond != 0)
+ return 1025l;
+ return x;
+}
+
+int
+not_int_long (int x, long cond)
+{
+ if (cond != 0)
+ return 1025;
+ return x;
+}
+
+long
+not_long_long (long x, int cond)
+{
+ if (cond != 0)
+ return 1025l;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
new file mode 100644
index 00000000000..732e892875b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (cond)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c
new file mode 100644
index 00000000000..e369a972a16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */
+
+int
+not_int_int (int x, int cond, int v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+long
+not_long_int (long x, int cond, long v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+int
+not_int_long (int x, long cond, int v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+long
+not_long_long (long x, int cond, long v)
+{
+ if (cond != 0)
+ return v;
+ return x;
+}
+
+/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */
--
2.38.1
