> -----原始邮件-----
> 发件人: "Jeff Law" <jeffreya...@gmail.com>
> 发送时间: 2022-11-21 23:26:37 (星期一)
> 收件人: "juzhe.zh...@rivai.ai" <juzhe.zh...@rivai.ai>, schwab
<sch...@linux-m68k.org>
> 抄送: gcc-patches <gcc-patches@gcc.gnu.org>, "monk.chiang"
<monk.chi...@sifive.com>, "kito.cheng" <kito.ch...@gmail.com>, jiawei
<jia...@iscas.ac.cn>
> 主题: Re: [PATCH] RISC-V: Add RVV registers register spilling
>
>
> On 11/21/22 02:25, juzhe.zh...@rivai.ai wrote:
> > https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606523.html
> > This patch obviously didn't include scalable size frame.
> > So it ICE in offset =
cfun->machine->frame.gp_sp_offset.to_constant ();
> > We can't directly use to_constant if the frame is a scalable.
> > Please fix it or revert it. Thanks
>
> We probably just need to reject everything in
> riscv_get_setparate_components if the offset isn't constant. Something
> like the attached patch (untested) might be enough to resolve the problem.
>
>
> Jeff
>
I tested this patch and it fix that problem and works well,
thanks for you works!
Jiawei
</jia...@iscas.ac.cn></kito.ch...@gmail.com></monk.chi...@sifive.com></gcc-patches@gcc.gnu.org></sch...@linux-m68k.org></juzhe.zh...@rivai.ai></jeffreya...@gmail.com>