Re: Re: [PATCH] RISC-V: Add RVV registers register spilling

[jiawei]

> -----原始邮件-----
&gt; 发件人: "Jeff Law" <jeffreya...@gmail.com>
&gt; 发送时间: 2022-11-21 23:26:37 (星期一)
&gt; 收件人: "juzhe.zh...@rivai.ai" <juzhe.zh...@rivai.ai>, schwab 
<sch...@linux-m68k.org>
&gt; 抄送: gcc-patches <gcc-patches@gcc.gnu.org>, "monk.chiang" 
<monk.chi...@sifive.com>, "kito.cheng" <kito.ch...@gmail.com>, jiawei 
<jia...@iscas.ac.cn>
&gt; 主题: Re: [PATCH] RISC-V: Add RVV registers register spilling
&gt; 
&gt; 
&gt; On 11/21/22 02:25, juzhe.zh...@rivai.ai wrote:
&gt; &gt; https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606523.html
&gt; &gt; This patch obviously didn't include scalable size frame.
&gt; &gt; So it ICE in offset = 
cfun-&gt;machine-&gt;frame.gp_sp_offset.to_constant ();
&gt; &gt; We can't directly use to_constant if the frame is a scalable.
&gt; &gt; Please fix it or revert it. Thanks
&gt; 
&gt; We probably just need to reject everything in 
&gt; riscv_get_setparate_components if the offset isn't constant. Something 
&gt; like the attached patch (untested) might be enough to resolve the problem.
&gt; 
&gt; 
&gt; Jeff
&gt; 

I tested this patch and it fix that problem and works well, 
thanks for you works!

Jiawei
</jia...@iscas.ac.cn></kito.ch...@gmail.com></monk.chi...@sifive.com></gcc-patches@gcc.gnu.org></sch...@linux-m68k.org></juzhe.zh...@rivai.ai></jeffreya...@gmail.com>