From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai> Sorry for resend this patch, I found I miss commit a file. 1. vector.md: remove tail && mask policy operand for mask mode operations since we don't need them according to RVV ISA. 2. riscv-v.cc: adapt emit_pred_op for mask mode predicated mov since all RVV modes including vector integer mode && vector float mode && vector bool mode are all use emit_pred_op function. For vector integer mode && vector float mode, we have instruction like vle.v/vse.v that we need tail && mask policy. However, for vector bool mode, the instruction is vlm/vsm that we don't need tail && mask policy. So we add a condition here to add tail && mask policy operand during expand if it is not a vector bool modes.
This patch is to cleanup the code and make it be consistent with RVV ISA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_pred_op): Adapt for mask mode. * config/riscv/vector.md: Remove Tail && make policy operand for mask mode mov. --- gcc/config/riscv/riscv-v.cc | 3 ++- gcc/config/riscv/vector.md | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d54795694f1..4992ff2470c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -136,7 +136,8 @@ emit_pred_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode) rtx vlmax = emit_vlmax_vsetvl (mode); e.add_input_operand (vlmax, Pmode); - e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); + if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL) + e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src)); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3bb87232d3f..38da2f7f095 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -593,8 +593,6 @@ (unspec:VB [(match_operand:VB 1 "vector_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VB 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1") -- 2.36.1