The (proposed, but about to be frozen) Zicond extension adds 2 unconditional R-type instructions that can be used to build branchless sequences that have conditional-arithmetic/bitwise/select semantics and integrate will with the RISC-V architecture.
See the Zicond specification for details: https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230207/riscv-zicond_1.0-draft-20230207.pdf The Zicond extension defines a conditional-zero(-or-value) instruction, which is similar to the following C construct: rd = rc ? rs : 0 This functionality can be tied back into if-convertsion and also matches some typical programming idioms. This series includes backend support for Zicond both to handle conditional-zero constructions and if-conversion. We also change the previously submitted XVentanaCondops support to use the Zicond infrastructure. Tested against SPEC CPU 2017. Philipp Tomsich (10): docs: Document a canonical RTL for a conditional-zero insns RISC-V: Recognize Zicond (conditional operations) extension RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion RISC-V: Support immediates in Zicond RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez RISC-V: Recognize sign-extract + and cases for czero.eqz/nez RISC-V: Recognize bexti in negated if-conversion ifcvt: add if-conversion to conditional-zero instructions RISC-V: Recognize xventanacondops extension RISC-V: Support XVentanaCondOps extension gcc/common/config/riscv/riscv-common.cc | 5 + gcc/config/riscv/predicates.md | 12 + gcc/config/riscv/riscv-opts.h | 5 + gcc/config/riscv/riscv.cc | 15 ++ gcc/config/riscv/riscv.md | 28 +++ gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/xventanacondops.md | 29 +++ gcc/config/riscv/zicond.md | 156 +++++++++++++ gcc/doc/md.texi | 17 ++ gcc/ifcvt.cc | 216 ++++++++++++++++++ .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ .../riscv/xventanacondops-ifconv-imm.c | 19 ++ .../gcc.target/riscv/xventanacondops-le-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-le-02.c | 11 + .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-lt-03.c | 16 ++ .../gcc.target/riscv/xventanacondops-ne-01.c | 10 + .../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++ .../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++ .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ .../gcc.target/riscv/zicond-and-01.c | 16 ++ .../gcc.target/riscv/zicond-and-02.c | 15 ++ gcc/testsuite/gcc.target/riscv/zicond-eq-01.c | 11 + gcc/testsuite/gcc.target/riscv/zicond-eq-02.c | 14 ++ .../gcc.target/riscv/zicond-ifconv-imm.c | 19 ++ gcc/testsuite/gcc.target/riscv/zicond-le-01.c | 16 ++ gcc/testsuite/gcc.target/riscv/zicond-le-02.c | 11 + gcc/testsuite/gcc.target/riscv/zicond-lt-01.c | 16 ++ gcc/testsuite/gcc.target/riscv/zicond-lt-03.c | 16 ++ gcc/testsuite/gcc.target/riscv/zicond-ne-01.c | 10 + gcc/testsuite/gcc.target/riscv/zicond-ne-03.c | 13 ++ gcc/testsuite/gcc.target/riscv/zicond-ne-04.c | 13 ++ .../gcc.target/riscv/zicond-xor-01.c | 14 ++ 36 files changed, 854 insertions(+) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/config/riscv/zicond.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-xor-01.c -- 2.34.1