The test uses arm_hard_ok and arm_softfp_ok as if they were mutually
exclusive, but they test whether the corresponding -mfloat-abi= flag
is usable, not whether it is in effect, so it is possible for both to
pass, and then the test comes out with incorrect expectations
whichever the default float-abi is.
Separate the test into hard and softfp variants, and extend the softfp
variant to accept both ARM and Thumb opcodes; it unwarrantedly assumed
the latter.
Regstrapped on x86_64-linux-gnu.
Tested on arm-vxworks7 (gcc-12) and arm-eabi (trunk). Ok to install?
for gcc/testsuite/ChangeLog
PR target/51534
* gcc.target/arm/pr51534.c: Split softfp variant into...
* gcc.target/arm/pr51534s.c: ... this, and support ARM too.
---
gcc/testsuite/gcc.target/arm/pr51534.c | 9 ++--
gcc/testsuite/gcc.target/arm/pr51534s.c | 72 +++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arm/pr51534s.c
diff --git a/gcc/testsuite/gcc.target/arm/pr51534.c
b/gcc/testsuite/gcc.target/arm/pr51534.c
index 5e121f5fb9946..ba21259bee554 100644
--- a/gcc/testsuite/gcc.target/arm/pr51534.c
+++ b/gcc/testsuite/gcc.target/arm/pr51534.c
@@ -1,9 +1,9 @@
/* Test the vector comparison intrinsics when comparing to immediate zero.
*/
-/* { dg-do assemble } */
+/* { dg-do assemble { target { arm_hard_ok } } } */
/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-save-temps -O3" } */
+/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
/* { dg-add-options arm_neon } */
#include <arm_neon.h>
@@ -64,9 +64,8 @@ GEN_COND_TESTS(vceq)
/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" 4 } } */
/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" 4 } } */
/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" 4 } } */
-/* { dg-final { scan-assembler-times "vmov\.i32\[ \]+\[dD\]\[0-9\]+,
#0xffffffff" 3 { target { arm_hard_ok } } } } */
-/* { dg-final { scan-assembler-times "vmov\.i32\[ \]+\[qQ\]\[0-9\]+,
#4294967295" 3 { target { arm_hard_ok } } } } */
-/* { dg-final { scan-assembler-times "mov\[ \]+r\[0-9\]+, #-1" 6 { target {
arm_softfp_ok } } } } */
+/* { dg-final { scan-assembler-times "vmov\.i32\[ \]+\[dD\]\[0-9\]+,
#0xffffffff" 3 } } */
+/* { dg-final { scan-assembler-times "vmov\.i32\[ \]+\[qQ\]\[0-9\]+,
#4294967295" 3 } } */
/* And ensure we don't have unexpected output too. */
/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[
\]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
diff --git a/gcc/testsuite/gcc.target/arm/pr51534s.c
b/gcc/testsuite/gcc.target/arm/pr51534s.c
new file mode 100644
index 0000000000000..b1638919c2f75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr51534s.c
@@ -0,0 +1,72 @@
+/* Test the vector comparison intrinsics when comparing to immediate zero.
+ */
+
+/* { dg-do assemble { target { arm_softfp_ok } } } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -mfloat-abi=softfp -O3" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+#define GEN_TEST(T, D, C, R) \
+ R test_##C##_##T (T a) { return C (a, D (0)); }
+
+#define GEN_DOUBLE_TESTS(S, T, C) \
+ GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
+ GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T)
+
+#define GEN_QUAD_TESTS(S, T, C) \
+ GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
+ GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T)
+
+#define GEN_COND_TESTS(C) \
+ GEN_DOUBLE_TESTS (8, int8x8_t, C) \
+ GEN_DOUBLE_TESTS (16, int16x4_t, C) \
+ GEN_DOUBLE_TESTS (32, int32x2_t, C) \
+ GEN_QUAD_TESTS (8, int8x16_t, C) \
+ GEN_QUAD_TESTS (16, int16x8_t, C) \
+ GEN_QUAD_TESTS (32, int32x4_t, C)
+
+GEN_COND_TESTS(vcgt)
+GEN_COND_TESTS(vcge)
+GEN_COND_TESTS(vclt)
+GEN_COND_TESTS(vcle)
+GEN_COND_TESTS(vceq)
+
+/* Scan for expected outputs. */
+/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" 4 } } */
+/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" 4 } } */
+/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[dD\]\[0-9\]+,
\[dD\]\[0-9\]+, #0" 4 } } */
+/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" 4 } } */
+/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" 4 } } */
+/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[qQ\]\[0-9\]+,
\[qQ\]\[0-9\]+, #0" 4 } } */
+/* { dg-final { scan-assembler-times "mov\[ \]+r\[0-9\]+, #-1|mvn\[
\]+r\[0-9\]+, #0" 6 } } */
+
+/* And ensure we don't have unexpected output too. */
+/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[
\]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
+
+/* Tidy up. */
--
Alexandre Oliva, happy hacker https://FSFLA.org/blogs/lxo/
Free Software Activist GNU Toolchain Engineer
Disinformation flourishes because many people care deeply about injustice
but very few check the facts. Ask me about <https://stallmansupport.org>
