Hi Jeff:
We promised only to commit intrinsic implication and bug fix this
moment, so yes, those optimization and non-bug fix pattern turning
include this will all defer to gcc-14.
On Wed, Mar 15, 2023 at 2:02 AM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
>
>
> On 3/13/23 02:19, juzhe.zh...@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
> >
> > Co-authored-by: kito-cheng <kito.ch...@sifive.com>
> > Co-authored-by: kito-cheng <kito.ch...@gmail.com>
> >
> > Consider this case:
> > void f19 (void *base,void *base2,void *out,size_t vl, int n)
> > {
> > vuint64m8_t bindex = __riscv_vle64_v_u64m8 (base + 100, vl);
> > for (int i = 0; i < n; i++){
> > vbool8_t m = __riscv_vlm_v_b8 (base + i, vl);
> > vuint64m8_t v = __riscv_vluxei64_v_u64m8_m(m,base,bindex,vl);
> > vuint64m8_t v2 = __riscv_vle64_v_u64m8_tu (v, base2 + i, vl);
> > vint8m1_t v3 = __riscv_vluxei64_v_i8m1_m(m,base,v,vl);
> > vint8m1_t v4 = __riscv_vluxei64_v_i8m1_m(m,base,v2,vl);
> > __riscv_vse8_v_i8m1 (out + 100*i,v3,vl);
> > __riscv_vse8_v_i8m1 (out + 222*i,v4,vl);
> > }
> > }
> >
> > Due to the current unreasonable reg order, this case produce unnecessary
> > register spillings.
> >
> > Fix the order can help for RA.
> >
> > Signed-off-by: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
> > Co-authored-by: kito-cheng <kito.ch...@sifive.com>
> > Co-authored-by: kito-cheng <kito.ch...@gmail.com>
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.h (enum reg_class): Fix reg order.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/spill-1.c: Adapt test.
> > * gcc.target/riscv/rvv/base/spill-2.c: Ditto.
> > * gcc.target/riscv/rvv/base/spill-3.c: Ditto.
> > * gcc.target/riscv/rvv/base/spill-4.c: Ditto.
> > * gcc.target/riscv/rvv/base/spill-5.c: Ditto.
> > * gcc.target/riscv/rvv/base/spill-6.c: Ditto.
> > * gcc.target/riscv/rvv/base/spill-7.c: Ditto.
> Are you OK with deferring this to gcc-14?
>
> jeff
