committed as https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=6f6eba35b9f06d35ff7bea81969fe905a5584bdc
On Fri, Mar 10, 2023 at 4:09 PM <juzhe.zh...@rivai.ai> wrote: > > From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai> > > vfrsub_vf_m.cpp: In function 'int main()': > vfrsub_vf_m.cpp:5:43: error: invalid argument to built-in function > 5 | vbool32_t d = __riscv_vmflt_vf_f32m1_b32(c, b, 8); > | ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~ > during RTL pass: expand > vfrsub_vf_m.cpp:5:43: internal compiler error: Segmentation fault > 0x19f1b89 crash_signal > ../../../../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/toplev.cc:314 > 0x1472e2f store_expr(tree_node*, rtx_def*, int, bool, bool) > ../../../../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/expr.cc:6348 > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc > (function_expander::use_compare_insn): Add operand predicate check. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/bug-1.c: New test. > > --- > gcc/config/riscv/riscv-vector-builtins.cc | 9 +++ > .../gcc.target/riscv/rvv/base/bug-1.c | 79 +++++++++++++++++++ > 2 files changed, 88 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c > > diff --git a/gcc/config/riscv/riscv-vector-builtins.cc > b/gcc/config/riscv/riscv-vector-builtins.cc > index fcda3863576..75e65091db3 100644 > --- a/gcc/config/riscv/riscv-vector-builtins.cc > +++ b/gcc/config/riscv/riscv-vector-builtins.cc > @@ -3084,6 +3084,15 @@ function_expander::use_compare_insn (rtx_code rcode, > insn_code icode) > > rtx op1 = expand_normal (CALL_EXPR_ARG (exp, arg_offset++)); > rtx op2 = expand_normal (CALL_EXPR_ARG (exp, arg_offset++)); > + if (!insn_operand_matches (icode, opno + 1, op1)) > + op1 = force_reg (mode, op1); > + if (!insn_operand_matches (icode, opno + 2, op2)) > + { > + if (VECTOR_MODE_P (GET_MODE (op2))) > + op2 = force_reg (mode, op2); > + else > + op2 = force_reg (GET_MODE_INNER (mode), op2); > + } > rtx comparison = gen_rtx_fmt_ee (rcode, mask_mode, op1, op2); > if (!VECTOR_MODE_P (GET_MODE (op2))) > comparison = gen_rtx_fmt_ee (rcode, mask_mode, op1, > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c > new file mode 100644 > index 00000000000..a8843674e31 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c > @@ -0,0 +1,79 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */ > + > +#include "riscv_vector.h" > + > +int > +f0 () > +{ > + float b; > + vfloat32m1_t c; > + vbool32_t d = __riscv_vmflt_vf_f32m1_b32 (c, b, 8); > + return 0; > +} > + > +int > +f1 () > +{ > + vfloat32m1_t c; > + vbool32_t d = __riscv_vmflt_vf_f32m1_b32 (c, 0, 8); > + return 0; > +} > + > +int > +f2 () > +{ > + vfloat32m1_t c; > + vbool32_t d = __riscv_vmflt_vf_f32m1_b32 (c, 55.55, 8); > + return 0; > +} > + > +int > +f3 () > +{ > + int32_t b; > + vint32m1_t c; > + vbool32_t d = __riscv_vmseq_vx_i32m1_b32 (c, b, 8); > + return 0; > +} > + > +int > +f4 () > +{ > + vint32m1_t c; > + vbool32_t d = __riscv_vmseq_vx_i32m1_b32 (c, 11, 8); > + return 0; > +} > + > +int > +f5 () > +{ > + int64_t b; > + vint64m1_t c; > + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, b, 8); > + return 0; > +} > + > +int > +f6 () > +{ > + vint64m1_t c; > + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, 11, 8); > + return 0; > +} > + > +int > +f7 () > +{ > + vint64m1_t c; > + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, 0xAAAA, 8); > + return 0; > +} > + > +int > +f8 () > +{ > + vint64m1_t c; > + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, 0xAAAAAAAAAAAAAA, 8); > + return 0; > +} > -- > 2.36.3 >