Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-05 Patrick O'Neill <patr...@rivosinc.com>
* riscv.cc (riscv_memmodel_needs_amo_acquire): Change function
name.
* riscv.cc (riscv_print_operand): Remove unneeded %F case.
* sync.md: Remove unneeded fences.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
gcc/config/riscv/riscv.cc | 16 +++++-----------
gcc/config/riscv/sync.md | 16 ++++++++--------
2 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8ffee494fbe..6576e9ae524 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4301,11 +4301,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
}
}
-/* Return true if a FENCE should be emitted to before a memory access to
- implement the release portion of memory model MODEL. */
+/* Return true if the .RL suffix should be added to an AMO to implement the
+ release portion of memory model MODEL. */
static bool
-riscv_memmodel_needs_release_fence (enum memmodel model)
+riscv_memmodel_needs_amo_release (enum memmodel model)
{
switch (model)
{
@@ -4331,7 +4331,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
'R' Print the low-part relocation associated with OP.
'C' Print the integer branch condition for comparison OP.
'A' Print the atomic operation suffix for memory model OP.
- 'F' Print a FENCE if the memory model requires a release.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
@@ -4493,19 +4492,14 @@ riscv_print_operand (FILE *file, rtx op, int letter)
case 'A':
if (riscv_memmodel_needs_amo_acquire (model) &&
- riscv_memmodel_needs_release_fence (model))
+ riscv_memmodel_needs_amo_release (model))
fputs (".aqrl", file);
else if (riscv_memmodel_needs_amo_acquire (model))
fputs (".aq", file);
- else if (riscv_memmodel_needs_release_fence (model))
+ else if (riscv_memmodel_needs_amo_release (model))
fputs (".rl", file);
break;
- case 'F':
- if (riscv_memmodel_needs_release_fence (model))
- fputs ("fence iorw,ow; ", file);
- break;
-
case 'i':
if (code != REG)
fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index de42245981b..1aa9ac81cee 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -61,9 +61,9 @@
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_ATOMIC_STORE))]
"TARGET_ATOMIC"
- "%F2amoswap.<amo>%A2 zero,%z1,%0"
+ "amoswap.<amo>%A2 zero,%z1,%0"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "atomic_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "memory_operand" "+A")
@@ -73,9 +73,9 @@
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
+ "amo<insn>.<amo>%A2 zero,%z1,%0"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "atomic_fetch_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -87,9 +87,9 @@
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
+ "amo<insn>.<amo>%A3 %0,%z2,%1"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "atomic_exchange<mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -100,9 +100,9 @@
(set (match_dup 1)
(match_operand:GPR 2 "register_operand" "0"))]
"TARGET_ATOMIC"
- "%F3amoswap.<amo>%A3 %0,%z2,%1"
+ "amoswap.<amo>%A3 %0,%z2,%1"
[(set_attr "type" "atomic")
- (set (attr "length") (const_int 8))])
+ (set (attr "length") (const_int 4))])
(define_insn "atomic_cas_value_strong<mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
--
2.25.1
