From: Yanzhang Wang <yanzhang.w...@intel.com>
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
PR 109104
gcc/ChangeLog:
* config/riscv/riscv-v.cc (default_zero_call_used_regs):
(riscv_zero_call_used_regs):
* config/riscv/riscv.cc (riscv_zero_call_used_regs):
(TARGET_ZERO_CALL_USED_REGS):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zero-scratch-regs-1.c: New test.
* gcc.target/riscv/zero-scratch-regs-2.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.w...@intel.com>
Co-authored-by: Pan Li <pan2...@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
Co-authored-by: Kito Cheng <kito.ch...@sifive.com>
---
gcc/config/riscv/riscv-v.cc | 79 +++++++++++++++++++
gcc/config/riscv/riscv.cc | 6 ++
.../gcc.target/riscv/zero-scratch-regs-1.c | 9 +++
.../gcc.target/riscv/zero-scratch-regs-2.c | 24 ++++++
4 files changed, 118 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2e91d019f6c..90c69b52bb4 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -43,6 +43,7 @@
#include "optabs.h"
#include "tm-constrs.h"
#include "rtx-vector-builder.h"
+#include "diagnostic-core.h"
using namespace riscv_vector;
@@ -724,4 +725,82 @@ gen_avl_for_scalar_move (rtx avl)
}
}
+/* Generate a sequence of instructions that zero registers specified by
+ NEED_ZEROED_HARDREGS. Return the ZEROED_HARDREGS that are actually
+ zeroed. */
+static HARD_REG_SET
+gpr_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+ HARD_REG_SET zeroed_hardregs;
+ CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+ for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; ++regno)
+ {
+ if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+ continue;
+
+ rtx reg = regno_reg_rtx[regno];
+ machine_mode mode = GET_MODE (reg);
+ emit_move_insn (reg, CONST0_RTX (mode));
+
+ SET_HARD_REG_BIT (zeroed_hardregs, regno);
+ }
+
+ return zeroed_hardregs;
+}
+
+static HARD_REG_SET
+vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+ HARD_REG_SET zeroed_hardregs;
+ CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+ /* Find a register to hold vl. */
+ unsigned vl_regno = GP_REG_LAST + 1;
+ for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+ {
+ /* If vl and avl both are x0, the existing vl is kept. */
+ if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno) && regno !=
X0_REGNUM)
+ {
+ vl_regno = regno;
+ break;
+ }
+ }
+
+ if (vl_regno > GP_REG_LAST)
+ sorry ("can't allocate vl register for %qs on this target",
+ "-fzero-call-used-regs");
+
+ rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX. */
+ for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
+ {
+ if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+ {
+ rtx target = regno_reg_rtx[regno];
+ machine_mode mode = GET_MODE (target);
+ poly_uint16 nunits = GET_MODE_NUNITS (mode);
+ machine_mode mask_mode = get_vector_mode (BImode, nunits).require ();
+
+ emit_vlmax_vsetvl (mode, vl);
+ emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode),
+ vl, mask_mode);
+
+ SET_HARD_REG_BIT (zeroed_hardregs, regno);
+ }
+ }
+
+ return zeroed_hardregs;
+}
+
+HARD_REG_SET
+riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+ HARD_REG_SET zeroed_hardregs;
+ CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+ if (TARGET_VECTOR)
+ zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
+
+ return zeroed_hardregs | gpr_zero_call_used_regs (need_zeroed_hardregs);
+}
} // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..e176f2d9f34 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT
mask)
#undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
#define TARGET_DWARF_POLY_INDETERMINATE_VALUE
riscv_dwarf_poly_indeterminate_value
+namespace riscv_vector {
+extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
+}
+#undef TARGET_ZERO_CALL_USED_REGS
+#define TARGET_ZERO_CALL_USED_REGS riscv_vector::riscv_zero_call_used_regs
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..2d9dfeb9dc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC"
} */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "li\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
new file mode 100644
index 00000000000..a53f034b5d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "vsetvli" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
--
2.39.2
