Re: [PATCH] dse: Handle SUBREGs of word REGs differently for WORD_REGISTER_OPERATIONS targets [PR109040]

[Jeff Law via Gcc-patches]

On 4/6/23 03:37, Li, Pan2 wrote:
Yes, RISC-V riscv.h defined the WORD_REGISTER_OPERATIONS to be 1, while 
aarch64.h defined it as 0, with below comments. No idea this can fit RISC-V or 
not.
I don't see any fundamental reason why it won't work.  Most of the 
expansion code already has code to widen types as necessary.  And given 
that we have a subset of 32bit ops, even in 64bit modes makes a 
WORD_REGISTER_OPERATIONS 0 a more sensible choice.

Jeff