You included asm output by accidently :P
On Thu, Apr 6, 2023 at 10:45 PM <juzhe.zh...@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zh...@rivai.ai>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/rvv.exp: Add testing for RVV
> auto-vectorization.
> * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Adapt testcase.
> * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: New test.
> * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.h: New test.
> * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: New test.
> * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h: New test.
> * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.s: New test.
> * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: New
> test.
> * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: New
> test.
> * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: New test.
> * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h: New test.
> * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: New
> test.
> * gcc.target/riscv/rvv/autovec/template-1.h: New test.
> * gcc.target/riscv/rvv/autovec/v-1.c: New test.
> * gcc.target/riscv/rvv/autovec/v-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x-2.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: New test.
> * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: New test.
>
> ---
> .../rvv/autovec/partial/multiple_rgroup-1.c | 6 +
> .../rvv/autovec/partial/multiple_rgroup-1.h | 304 +++++++
> .../rvv/autovec/partial/multiple_rgroup-2.c | 6 +
> .../rvv/autovec/partial/multiple_rgroup-2.h | 546 ++++++++++++
> .../rvv/autovec/partial/multiple_rgroup-2.s | 774 ++++++++++++++++++
> .../autovec/partial/multiple_rgroup_run-1.c | 19 +
> .../autovec/partial/multiple_rgroup_run-2.c | 19 +
> .../rvv/autovec/partial/single_rgroup-1.c | 8 +
> .../rvv/autovec/partial/single_rgroup-1.h | 106 +++
> .../rvv/autovec/partial/single_rgroup_run-1.c | 19 +
> .../gcc.target/riscv/rvv/autovec/template-1.h | 68 ++
> .../gcc.target/riscv/rvv/autovec/v-1.c | 4 +
> .../gcc.target/riscv/rvv/autovec/v-2.c | 6 +
> .../gcc.target/riscv/rvv/autovec/zve32f-1.c | 4 +
> .../gcc.target/riscv/rvv/autovec/zve32f-2.c | 5 +
> .../riscv/rvv/autovec/zve32f_zvl128b-1.c | 4 +
> .../riscv/rvv/autovec/zve32f_zvl128b-2.c | 6 +
> .../gcc.target/riscv/rvv/autovec/zve32x-1.c | 4 +
> .../gcc.target/riscv/rvv/autovec/zve32x-2.c | 6 +
> .../riscv/rvv/autovec/zve32x_zvl128b-1.c | 5 +
> .../riscv/rvv/autovec/zve32x_zvl128b-2.c | 6 +
> .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 4 +
> .../gcc.target/riscv/rvv/autovec/zve64d-2.c | 4 +
> .../riscv/rvv/autovec/zve64d_zvl128b-1.c | 4 +
> .../riscv/rvv/autovec/zve64d_zvl128b-2.c | 6 +
> .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 4 +
> .../gcc.target/riscv/rvv/autovec/zve64f-2.c | 4 +
> .../riscv/rvv/autovec/zve64f_zvl128b-1.c | 4 +
> .../riscv/rvv/autovec/zve64f_zvl128b-2.c | 6 +
> .../gcc.target/riscv/rvv/autovec/zve64x-1.c | 4 +
> .../gcc.target/riscv/rvv/autovec/zve64x-2.c | 4 +
> .../riscv/rvv/autovec/zve64x_zvl128b-1.c | 4 +
> .../riscv/rvv/autovec/zve64x_zvl128b-2.c | 6 +
> gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 16 +
> .../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c | 2 +-
> 35 files changed, 1996 insertions(+), 1 deletion(-)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.h
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.s
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
>
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
> new file mode 100644
> index 00000000000..69cc3be78f7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax" } */
> +
> +#include "multiple_rgroup-1.h"
> +
> +TEST_ALL (test_1)
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.h
> new file mode 100644
> index 00000000000..755ee2b3616
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.h
> @@ -0,0 +1,304 @@
> +#include <stddef.h>
> +#include <stdint.h>
> +
> +#define test_1(TYPE1, TYPE2)
> \
> + void __attribute__ ((noinline, noclone))
> \
> + test_1_##TYPE1_##TYPE2 (TYPE1 *__restrict f, TYPE2 *__restrict d, TYPE1 x,
> \
> + TYPE1 x2, TYPE2 y, int n)
> \
> + {
> \
> + for (int i = 0; i < n; ++i)
> \
> + {
> \
> + f[i * 2 + 0] = x;
> \
> + f[i * 2 + 1] = x2;
> \
> + d[i] = y;
> \
> + }
> \
> + }
> +
> +#define run_1(TYPE1, TYPE2)
> \
> + int n_1_##TYPE1_##TYPE2 = 1;
> \
> + TYPE1 x_1_##TYPE1 = 117;
> \
> + TYPE1 x2_1_##TYPE1 = 232;
> \
> + TYPE2 y_1_##TYPE2 = 9762;
> \
> + TYPE1 f_1_##TYPE1[2 * 2 + 1] = {0};
> \
> + TYPE2 d_1_##TYPE2[2] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_1_##TYPE1, d_1_##TYPE2, x_1_##TYPE1,
> x2_1_##TYPE1, \
> + y_1_##TYPE2, n_1_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_1_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_1_##TYPE1[i * 2 + 0] != x_1_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 2 + 1] != x2_1_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_1_##TYPE2[i] != y_1_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_1_##TYPE1_##TYPE2; i < n_1_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_1_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_1_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_2(TYPE1, TYPE2)
> \
> + int n_2_##TYPE1_##TYPE2 = 17;
> \
> + TYPE1 x_2_##TYPE1 = 133;
> \
> + TYPE1 x2_2_##TYPE1 = 94;
> \
> + TYPE2 y_2_##TYPE2 = 8672;
> \
> + TYPE1 f_2_##TYPE1[18 * 2 + 1] = {0};
> \
> + TYPE2 d_2_##TYPE2[18] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_2_##TYPE1, d_2_##TYPE2, x_2_##TYPE1,
> x2_2_##TYPE1, \
> + y_2_##TYPE2, n_2_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_2_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_2_##TYPE1[i * 2 + 0] != x_2_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 2 + 1] != x2_2_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_2_##TYPE2[i] != y_2_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_2_##TYPE1_##TYPE2; i < n_2_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_2_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_2_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_3(TYPE1, TYPE2)
> \
> + int n_3_##TYPE1_##TYPE2 = 32;
> \
> + TYPE1 x_3_##TYPE1 = 233;
> \
> + TYPE1 x2_3_##TYPE1 = 78;
> \
> + TYPE2 y_3_##TYPE2 = 1234;
> \
> + TYPE1 f_3_##TYPE1[33 * 2 + 1] = {0};
> \
> + TYPE2 d_3_##TYPE2[33] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_3_##TYPE1, d_3_##TYPE2, x_3_##TYPE1,
> x2_3_##TYPE1, \
> + y_3_##TYPE2, n_3_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_3_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_3_##TYPE1[i * 2 + 0] != x_3_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 2 + 1] != x2_3_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_3_##TYPE2[i] != y_3_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_3_##TYPE1_##TYPE2; i < n_3_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_3_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_3_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_4(TYPE1, TYPE2)
> \
> + int n_4_##TYPE1_##TYPE2 = 128;
> \
> + TYPE1 x_4_##TYPE1 = 222;
> \
> + TYPE1 x2_4_##TYPE1 = 59;
> \
> + TYPE2 y_4_##TYPE2 = 4321;
> \
> + TYPE1 f_4_##TYPE1[129 * 2 + 1] = {0};
> \
> + TYPE2 d_4_##TYPE2[129] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_4_##TYPE1, d_4_##TYPE2, x_4_##TYPE1,
> x2_4_##TYPE1, \
> + y_4_##TYPE2, n_4_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_4_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_4_##TYPE1[i * 2 + 0] != x_4_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 2 + 1] != x2_4_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_4_##TYPE2[i] != y_4_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_4_##TYPE1_##TYPE2; i < n_4_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_4_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_4_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_5(TYPE1, TYPE2)
> \
> + int n_5_##TYPE1_##TYPE2 = 177;
> \
> + TYPE1 x_5_##TYPE1 = 111;
> \
> + TYPE1 x2_5_##TYPE1 = 189;
> \
> + TYPE2 y_5_##TYPE2 = 5555;
> \
> + TYPE1 f_5_##TYPE1[178 * 2 + 1] = {0};
> \
> + TYPE2 d_5_##TYPE2[178] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_5_##TYPE1, d_5_##TYPE2, x_5_##TYPE1,
> x2_5_##TYPE1, \
> + y_5_##TYPE2, n_5_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_5_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_5_##TYPE1[i * 2 + 0] != x_5_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 2 + 1] != x2_5_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_5_##TYPE2[i] != y_5_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_5_##TYPE1_##TYPE2; i < n_5_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_5_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_5_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_6(TYPE1, TYPE2)
> \
> + int n_6_##TYPE1_##TYPE2 = 255;
> \
> + TYPE1 x_6_##TYPE1 = 123;
> \
> + TYPE1 x2_6_##TYPE1 = 132;
> \
> + TYPE2 y_6_##TYPE2 = 6655;
> \
> + TYPE1 f_6_##TYPE1[256 * 2 + 1] = {0};
> \
> + TYPE2 d_6_##TYPE2[256] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_6_##TYPE1, d_6_##TYPE2, x_6_##TYPE1,
> x2_6_##TYPE1, \
> + y_6_##TYPE2, n_6_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_6_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_6_##TYPE1[i * 2 + 0] != x_6_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 2 + 1] != x2_6_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_6_##TYPE2[i] != y_6_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_6_##TYPE1_##TYPE2; i < n_6_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_6_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_6_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_7(TYPE1, TYPE2)
> \
> + int n_7_##TYPE1_##TYPE2 = 333;
> \
> + TYPE1 x_7_##TYPE1 = 39;
> \
> + TYPE1 x2_7_##TYPE1 = 59;
> \
> + TYPE2 y_7_##TYPE2 = 5968;
> \
> + TYPE1 f_7_##TYPE1[334 * 2 + 1] = {0};
> \
> + TYPE2 d_7_##TYPE2[334] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_7_##TYPE1, d_7_##TYPE2, x_7_##TYPE1,
> x2_7_##TYPE1, \
> + y_7_##TYPE2, n_7_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_7_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_7_##TYPE1[i * 2 + 0] != x_7_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 2 + 1] != x2_7_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_7_##TYPE2[i] != y_7_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_7_##TYPE1_##TYPE2; i < n_7_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_7_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_7_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_8(TYPE1, TYPE2)
> \
> + int n_8_##TYPE1_##TYPE2 = 512;
> \
> + TYPE1 x_8_##TYPE1 = 71;
> \
> + TYPE1 x2_8_##TYPE1 = 255;
> \
> + TYPE2 y_8_##TYPE2 = 3366;
> \
> + TYPE1 f_8_##TYPE1[513 * 2 + 1] = {0};
> \
> + TYPE2 d_8_##TYPE2[513] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_8_##TYPE1, d_8_##TYPE2, x_8_##TYPE1,
> x2_8_##TYPE1, \
> + y_8_##TYPE2, n_8_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_8_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_8_##TYPE1[i * 2 + 0] != x_8_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 2 + 1] != x2_8_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_8_##TYPE2[i] != y_8_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_8_##TYPE1_##TYPE2; i < n_8_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_8_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_8_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_9(TYPE1, TYPE2)
> \
> + int n_9_##TYPE1_##TYPE2 = 637;
> \
> + TYPE1 x_9_##TYPE1 = 157;
> \
> + TYPE1 x2_9_##TYPE1 = 89;
> \
> + TYPE2 y_9_##TYPE2 = 5511;
> \
> + TYPE1 f_9_##TYPE1[638 * 2 + 1] = {0};
> \
> + TYPE2 d_9_##TYPE2[638] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_9_##TYPE1, d_9_##TYPE2, x_9_##TYPE1,
> x2_9_##TYPE1, \
> + y_9_##TYPE2, n_9_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_9_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_9_##TYPE1[i * 2 + 0] != x_9_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 2 + 1] != x2_9_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_9_##TYPE2[i] != y_9_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_9_##TYPE1_##TYPE2; i < n_9_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_9_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_9_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_10(TYPE1, TYPE2)
> \
> + int n_10_##TYPE1_##TYPE2 = 777;
> \
> + TYPE1 x_10_##TYPE1 = 203;
> \
> + TYPE1 x2_10_##TYPE1 = 200;
> \
> + TYPE2 y_10_##TYPE2 = 2023;
> \
> + TYPE1 f_10_##TYPE1[778 * 2 + 1] = {0};
> \
> + TYPE2 d_10_##TYPE2[778] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_10_##TYPE1, d_10_##TYPE2, x_10_##TYPE1,
> \
> + x2_10_##TYPE1, y_10_##TYPE2, n_10_##TYPE1_##TYPE2);
> \
> + for (int i = 0; i < n_10_##TYPE1_##TYPE2; ++i)
> \
> + {
> \
> + if (f_10_##TYPE1[i * 2 + 0] != x_10_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 2 + 1] != x2_10_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_10_##TYPE2[i] != y_10_##TYPE2)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_10_##TYPE1_##TYPE2; i < n_10_##TYPE1_##TYPE2 + 1; ++i)
> \
> + {
> \
> + if (f_10_##TYPE1[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_10_##TYPE2[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define TEST_ALL(T)
> \
> + T (int8_t, int16_t)
> \
> + T (uint8_t, uint16_t)
> \
> + T (int16_t, int32_t)
> \
> + T (uint16_t, uint32_t)
> \
> + T (int32_t, int64_t)
> \
> + T (uint32_t, uint64_t)
> \
> + T (float, double)
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
> new file mode 100644
> index 00000000000..d1c41907547
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax" } */
> +
> +#include "multiple_rgroup-2.h"
> +
> +TEST_ALL (test_1)
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h
> new file mode 100644
> index 00000000000..aa50726697c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h
> @@ -0,0 +1,546 @@
> +#include <stddef.h>
> +#include <stdint.h>
> +
> +#define test_1(TYPE1, TYPE2, TYPE3)
> \
> + void __attribute__ ((noinline, noclone))
> \
> + test_1_##TYPE1_##TYPE2 (TYPE1 *__restrict f, TYPE2 *__restrict d,
> \
> + TYPE3 *__restrict e, TYPE1 x, TYPE1 x2, TYPE1 x3,
> \
> + TYPE1 x4, TYPE2 y, TYPE2 y2, TYPE3 z, int n)
> \
> + {
> \
> + for (int i = 0; i < n; ++i)
> \
> + {
> \
> + f[i * 4 + 0] = x;
> \
> + f[i * 4 + 1] = x2;
> \
> + f[i * 4 + 2] = x3;
> \
> + f[i * 4 + 3] = x4;
> \
> + d[i * 2 + 0] = y;
> \
> + d[i * 2 + 1] = y2;
> \
> + e[i] = z;
> \
> + }
> \
> + }
> +
> +#define run_1(TYPE1, TYPE2, TYPE3)
> \
> + int n_1_##TYPE1_##TYPE2_##TYPE3 = 1;
> \
> + TYPE1 x_1_##TYPE1 = 117;
> \
> + TYPE1 x2_1_##TYPE1 = 232;
> \
> + TYPE1 x3_1_##TYPE1 = 127;
> \
> + TYPE1 x4_1_##TYPE1 = 11;
> \
> + TYPE2 y_1_##TYPE2 = 9762;
> \
> + TYPE2 y2_1_##TYPE2 = 6279;
> \
> + TYPE3 z_1_##TYPE3 = 5891663;
> \
> + TYPE1 f_1_##TYPE1[2 * 4 + 1] = {0};
> \
> + TYPE2 d_1_##TYPE2[2 * 2 + 1] = {0};
> \
> + TYPE3 e_1_##TYPE3[2] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_1_##TYPE1, d_1_##TYPE2, e_1_##TYPE3,
> x_1_##TYPE1, \
> + x2_1_##TYPE1, x3_1_##TYPE1, x4_1_##TYPE1,
> \
> + y_1_##TYPE2, y2_1_##TYPE2, z_1_##TYPE3,
> \
> + n_1_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_1_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_1_##TYPE1[i * 4 + 0] != x_1_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 4 + 1] != x2_1_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 4 + 2] != x3_1_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 4 + 3] != x4_1_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_1_##TYPE2[i * 2 + 0] != y_1_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_1_##TYPE2[i * 2 + 1] != y2_1_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_1_##TYPE3[i] != z_1_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_1_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_1_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_1_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_1_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_1_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_1_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_1_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_2(TYPE1, TYPE2, TYPE3)
> \
> + int n_2_##TYPE1_##TYPE2_##TYPE3 = 17;
> \
> + TYPE1 x_2_##TYPE1 = 107;
> \
> + TYPE1 x2_2_##TYPE1 = 202;
> \
> + TYPE1 x3_2_##TYPE1 = 17;
> \
> + TYPE1 x4_2_##TYPE1 = 53;
> \
> + TYPE2 y_2_##TYPE2 = 5566;
> \
> + TYPE2 y2_2_##TYPE2 = 7926;
> \
> + TYPE3 z_2_##TYPE3 = 781545971;
> \
> + TYPE1 f_2_##TYPE1[18 * 4 + 1] = {0};
> \
> + TYPE2 d_2_##TYPE2[18 * 2 + 1] = {0};
> \
> + TYPE3 e_2_##TYPE3[18] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_2_##TYPE1, d_2_##TYPE2, e_2_##TYPE3,
> x_2_##TYPE1, \
> + x2_2_##TYPE1, x3_2_##TYPE1, x4_2_##TYPE1,
> \
> + y_2_##TYPE2, y2_2_##TYPE2, z_2_##TYPE3,
> \
> + n_2_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_2_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_2_##TYPE1[i * 4 + 0] != x_2_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 4 + 1] != x2_2_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 4 + 2] != x3_2_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 4 + 3] != x4_2_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_2_##TYPE2[i * 2 + 0] != y_2_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_2_##TYPE2[i * 2 + 1] != y2_2_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_2_##TYPE3[i] != z_2_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_2_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_2_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_2_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_2_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_2_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_2_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_2_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_3(TYPE1, TYPE2, TYPE3)
> \
> + int n_3_##TYPE1_##TYPE2_##TYPE3 = 32;
> \
> + TYPE1 x_3_##TYPE1 = 109;
> \
> + TYPE1 x2_3_##TYPE1 = 239;
> \
> + TYPE1 x3_3_##TYPE1 = 151;
> \
> + TYPE1 x4_3_##TYPE1 = 3;
> \
> + TYPE2 y_3_##TYPE2 = 1234;
> \
> + TYPE2 y2_3_##TYPE2 = 4321;
> \
> + TYPE3 z_3_##TYPE3 = 145615615;
> \
> + TYPE1 f_3_##TYPE1[33 * 4 + 1] = {0};
> \
> + TYPE2 d_3_##TYPE2[33 * 2 + 1] = {0};
> \
> + TYPE3 e_3_##TYPE3[33] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_3_##TYPE1, d_3_##TYPE2, e_3_##TYPE3,
> x_3_##TYPE1, \
> + x2_3_##TYPE1, x3_3_##TYPE1, x4_3_##TYPE1,
> \
> + y_3_##TYPE2, y2_3_##TYPE2, z_3_##TYPE3,
> \
> + n_3_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_3_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_3_##TYPE1[i * 4 + 0] != x_3_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 4 + 1] != x2_3_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 4 + 2] != x3_3_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 4 + 3] != x4_3_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_3_##TYPE2[i * 2 + 0] != y_3_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_3_##TYPE2[i * 2 + 1] != y2_3_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_3_##TYPE3[i] != z_3_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_3_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_3_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_3_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_3_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_3_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_3_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_3_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_4(TYPE1, TYPE2, TYPE3)
> \
> + int n_4_##TYPE1_##TYPE2_##TYPE3 = 128;
> \
> + TYPE1 x_4_##TYPE1 = 239;
> \
> + TYPE1 x2_4_##TYPE1 = 132;
> \
> + TYPE1 x3_4_##TYPE1 = 39;
> \
> + TYPE1 x4_4_##TYPE1 = 48;
> \
> + TYPE2 y_4_##TYPE2 = 1036;
> \
> + TYPE2 y2_4_##TYPE2 = 3665;
> \
> + TYPE3 z_4_##TYPE3 = 5145656;
> \
> + TYPE1 f_4_##TYPE1[129 * 4 + 1] = {0};
> \
> + TYPE2 d_4_##TYPE2[129 * 2 + 1] = {0};
> \
> + TYPE3 e_4_##TYPE3[129] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_4_##TYPE1, d_4_##TYPE2, e_4_##TYPE3,
> x_4_##TYPE1, \
> + x2_4_##TYPE1, x3_4_##TYPE1, x4_4_##TYPE1,
> \
> + y_4_##TYPE2, y2_4_##TYPE2, z_4_##TYPE3,
> \
> + n_4_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_4_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_4_##TYPE1[i * 4 + 0] != x_4_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 4 + 1] != x2_4_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 4 + 2] != x3_4_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 4 + 3] != x4_4_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_4_##TYPE2[i * 2 + 0] != y_4_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_4_##TYPE2[i * 2 + 1] != y2_4_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_4_##TYPE3[i] != z_4_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_4_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_4_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_4_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_4_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_4_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_4_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_4_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_5(TYPE1, TYPE2, TYPE3)
> \
> + int n_5_##TYPE1_##TYPE2_##TYPE3 = 177;
> \
> + TYPE1 x_5_##TYPE1 = 239;
> \
> + TYPE1 x2_5_##TYPE1 = 132;
> \
> + TYPE1 x3_5_##TYPE1 = 39;
> \
> + TYPE1 x4_5_##TYPE1 = 48;
> \
> + TYPE2 y_5_##TYPE2 = 1036;
> \
> + TYPE2 y2_5_##TYPE2 = 3665;
> \
> + TYPE3 z_5_##TYPE3 = 5145656;
> \
> + TYPE1 f_5_##TYPE1[178 * 4 + 1] = {0};
> \
> + TYPE2 d_5_##TYPE2[178 * 2 + 1] = {0};
> \
> + TYPE3 e_5_##TYPE3[178] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_5_##TYPE1, d_5_##TYPE2, e_5_##TYPE3,
> x_5_##TYPE1, \
> + x2_5_##TYPE1, x3_5_##TYPE1, x4_5_##TYPE1,
> \
> + y_5_##TYPE2, y2_5_##TYPE2, z_5_##TYPE3,
> \
> + n_5_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_5_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_5_##TYPE1[i * 4 + 0] != x_5_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 4 + 1] != x2_5_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 4 + 2] != x3_5_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 4 + 3] != x4_5_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_5_##TYPE2[i * 2 + 0] != y_5_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_5_##TYPE2[i * 2 + 1] != y2_5_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_5_##TYPE3[i] != z_5_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_5_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_5_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_5_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_5_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_5_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_5_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_5_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_6(TYPE1, TYPE2, TYPE3)
> \
> + int n_6_##TYPE1_##TYPE2_##TYPE3 = 255;
> \
> + TYPE1 x_6_##TYPE1 = 239;
> \
> + TYPE1 x2_6_##TYPE1 = 132;
> \
> + TYPE1 x3_6_##TYPE1 = 39;
> \
> + TYPE1 x4_6_##TYPE1 = 48;
> \
> + TYPE2 y_6_##TYPE2 = 1036;
> \
> + TYPE2 y2_6_##TYPE2 = 3665;
> \
> + TYPE3 z_6_##TYPE3 = 5145656;
> \
> + TYPE1 f_6_##TYPE1[256 * 4 + 1] = {0};
> \
> + TYPE2 d_6_##TYPE2[256 * 2 + 1] = {0};
> \
> + TYPE3 e_6_##TYPE3[256] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_6_##TYPE1, d_6_##TYPE2, e_6_##TYPE3,
> x_6_##TYPE1, \
> + x2_6_##TYPE1, x3_6_##TYPE1, x4_6_##TYPE1,
> \
> + y_6_##TYPE2, y2_6_##TYPE2, z_6_##TYPE3,
> \
> + n_6_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_6_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_6_##TYPE1[i * 4 + 0] != x_6_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 4 + 1] != x2_6_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 4 + 2] != x3_6_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 4 + 3] != x4_6_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_6_##TYPE2[i * 2 + 0] != y_6_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_6_##TYPE2[i * 2 + 1] != y2_6_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_6_##TYPE3[i] != z_6_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_6_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_6_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_6_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_6_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_6_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_6_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_6_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_7(TYPE1, TYPE2, TYPE3)
> \
> + int n_7_##TYPE1_##TYPE2_##TYPE3 = 333;
> \
> + TYPE1 x_7_##TYPE1 = 239;
> \
> + TYPE1 x2_7_##TYPE1 = 132;
> \
> + TYPE1 x3_7_##TYPE1 = 39;
> \
> + TYPE1 x4_7_##TYPE1 = 48;
> \
> + TYPE2 y_7_##TYPE2 = 1036;
> \
> + TYPE2 y2_7_##TYPE2 = 3665;
> \
> + TYPE3 z_7_##TYPE3 = 5145656;
> \
> + TYPE1 f_7_##TYPE1[334 * 4 + 1] = {0};
> \
> + TYPE2 d_7_##TYPE2[334 * 2 + 1] = {0};
> \
> + TYPE3 e_7_##TYPE3[334] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_7_##TYPE1, d_7_##TYPE2, e_7_##TYPE3,
> x_7_##TYPE1, \
> + x2_7_##TYPE1, x3_7_##TYPE1, x4_7_##TYPE1,
> \
> + y_7_##TYPE2, y2_7_##TYPE2, z_7_##TYPE3,
> \
> + n_7_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_7_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_7_##TYPE1[i * 4 + 0] != x_7_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 4 + 1] != x2_7_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 4 + 2] != x3_7_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 4 + 3] != x4_7_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_7_##TYPE2[i * 2 + 0] != y_7_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_7_##TYPE2[i * 2 + 1] != y2_7_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_7_##TYPE3[i] != z_7_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_7_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_7_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_7_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_7_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_7_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_7_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_7_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_8(TYPE1, TYPE2, TYPE3)
> \
> + int n_8_##TYPE1_##TYPE2_##TYPE3 = 512;
> \
> + TYPE1 x_8_##TYPE1 = 239;
> \
> + TYPE1 x2_8_##TYPE1 = 132;
> \
> + TYPE1 x3_8_##TYPE1 = 39;
> \
> + TYPE1 x4_8_##TYPE1 = 48;
> \
> + TYPE2 y_8_##TYPE2 = 1036;
> \
> + TYPE2 y2_8_##TYPE2 = 3665;
> \
> + TYPE3 z_8_##TYPE3 = 5145656;
> \
> + TYPE1 f_8_##TYPE1[513 * 4 + 1] = {0};
> \
> + TYPE2 d_8_##TYPE2[513 * 2 + 1] = {0};
> \
> + TYPE3 e_8_##TYPE3[513] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_8_##TYPE1, d_8_##TYPE2, e_8_##TYPE3,
> x_8_##TYPE1, \
> + x2_8_##TYPE1, x3_8_##TYPE1, x4_8_##TYPE1,
> \
> + y_8_##TYPE2, y2_8_##TYPE2, z_8_##TYPE3,
> \
> + n_8_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_8_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_8_##TYPE1[i * 4 + 0] != x_8_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 4 + 1] != x2_8_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 4 + 2] != x3_8_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 4 + 3] != x4_8_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_8_##TYPE2[i * 2 + 0] != y_8_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_8_##TYPE2[i * 2 + 1] != y2_8_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_8_##TYPE3[i] != z_8_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_8_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_8_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_8_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_8_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_8_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_8_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_8_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_9(TYPE1, TYPE2, TYPE3)
> \
> + int n_9_##TYPE1_##TYPE2_##TYPE3 = 637;
> \
> + TYPE1 x_9_##TYPE1 = 222;
> \
> + TYPE1 x2_9_##TYPE1 = 111;
> \
> + TYPE1 x3_9_##TYPE1 = 11;
> \
> + TYPE1 x4_9_##TYPE1 = 7;
> \
> + TYPE2 y_9_##TYPE2 = 2034;
> \
> + TYPE2 y2_9_##TYPE2 = 6987;
> \
> + TYPE3 z_9_##TYPE3 = 1564616;
> \
> + TYPE1 f_9_##TYPE1[638 * 4 + 1] = {0};
> \
> + TYPE2 d_9_##TYPE2[638 * 2 + 1] = {0};
> \
> + TYPE3 e_9_##TYPE3[638] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_9_##TYPE1, d_9_##TYPE2, e_9_##TYPE3,
> x_9_##TYPE1, \
> + x2_9_##TYPE1, x3_9_##TYPE1, x4_9_##TYPE1,
> \
> + y_9_##TYPE2, y2_9_##TYPE2, z_9_##TYPE3,
> \
> + n_9_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_9_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_9_##TYPE1[i * 4 + 0] != x_9_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 4 + 1] != x2_9_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 4 + 2] != x3_9_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 4 + 3] != x4_9_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_9_##TYPE2[i * 2 + 0] != y_9_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_9_##TYPE2[i * 2 + 1] != y2_9_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_9_##TYPE3[i] != z_9_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_9_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_9_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_9_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_9_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_9_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_9_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_9_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define run_10(TYPE1, TYPE2, TYPE3)
> \
> + int n_10_##TYPE1_##TYPE2_##TYPE3 = 777;
> \
> + TYPE1 x_10_##TYPE1 = 222;
> \
> + TYPE1 x2_10_##TYPE1 = 111;
> \
> + TYPE1 x3_10_##TYPE1 = 11;
> \
> + TYPE1 x4_10_##TYPE1 = 7;
> \
> + TYPE2 y_10_##TYPE2 = 2034;
> \
> + TYPE2 y2_10_##TYPE2 = 6987;
> \
> + TYPE3 z_10_##TYPE3 = 1564616;
> \
> + TYPE1 f_10_##TYPE1[778 * 4 + 1] = {0};
> \
> + TYPE2 d_10_##TYPE2[778 * 2 + 1] = {0};
> \
> + TYPE3 e_10_##TYPE3[778] = {0};
> \
> + test_1_##TYPE1_##TYPE2 (f_10_##TYPE1, d_10_##TYPE2, e_10_##TYPE3,
> x_10_##TYPE1, \
> + x2_10_##TYPE1, x3_10_##TYPE1, x4_10_##TYPE1,
> \
> + y_10_##TYPE2, y2_10_##TYPE2, z_10_##TYPE3,
> \
> + n_10_##TYPE1_##TYPE2_##TYPE3);
> \
> + for (int i = 0; i < n_10_##TYPE1_##TYPE2_##TYPE3; ++i)
> \
> + {
> \
> + if (f_10_##TYPE1[i * 4 + 0] != x_10_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 4 + 1] != x2_10_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 4 + 2] != x3_10_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 4 + 3] != x4_10_##TYPE1)
> \
> + __builtin_abort ();
> \
> + if (d_10_##TYPE2[i * 2 + 0] != y_10_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (d_10_##TYPE2[i * 2 + 1] != y2_10_##TYPE2)
> \
> + __builtin_abort ();
> \
> + if (e_10_##TYPE3[i] != z_10_##TYPE3)
> \
> + __builtin_abort ();
> \
> + }
> \
> + for (int i = n_10_##TYPE1_##TYPE2_##TYPE3;
> \
> + i < n_10_##TYPE1_##TYPE2_##TYPE3 + 1; ++i)
> \
> + {
> \
> + if (f_10_##TYPE1[i * 4 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 4 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 4 + 2] != 0)
> \
> + __builtin_abort ();
> \
> + if (f_10_##TYPE1[i * 4 + 3] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_10_##TYPE2[i * 2 + 0] != 0)
> \
> + __builtin_abort ();
> \
> + if (d_10_##TYPE2[i * 2 + 1] != 0)
> \
> + __builtin_abort ();
> \
> + if (e_10_##TYPE3[i] != 0)
> \
> + __builtin_abort ();
> \
> + }
> +
> +#define TEST_ALL(T)
> \
> + T (int8_t, int16_t, int32_t)
> \
> + T (uint8_t, uint16_t, uint32_t)
> \
> + T (int16_t, int32_t, int64_t)
> \
> + T (uint16_t, uint32_t, uint64_t)
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.s
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.s
> new file mode 100644
> index 00000000000..64b36fe5092
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.s
> @@ -0,0 +1,774 @@
> + .file "multiple_rgroup-2.c"
> + .option nopic
> + .attribute arch,
> "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
> + .attribute unaligned_access, 0
> + .attribute stack_align, 16
> + .text
> + .align 1
> + .globl test_1_TYPE1_int16_t
> + .type test_1_TYPE1_int16_t, @function
> +test_1_TYPE1_int16_t:
> + addi sp,sp,-48
> + lw t5,56(sp)
> + lh t3,48(sp)
> + lw t6,52(sp)
> + ble t5,zero,.L1
> + or t1,a2,a1
> + or t1,a0,t1
> + andi t1,t1,15
> + bne t1,zero,.L3
> + andi a4,a4,0xff
> + andi a3,a3,0xff
> + slli a4,a4,8
> + andi a5,a5,0xff
> + slli a5,a5,16
> + or t4,a3,a4
> + vsetvli t1,zero,e8,m1,ta,ma
> + li t2,16777216
> + addi t2,t2,-1
> + or t1,t4,a5
> + slli a6,a6,24
> + and t1,t1,t2
> + vmv.v.i v1,0
> + sw s0,44(sp)
> + vs1r.v v1,0(sp)
> + or s0,t1,a6
> + sw s0,0(sp)
> + lw s0,4(sp)
> + li t4,-65536
> + addi t4,t4,255
> + andi t0,s0,-256
> + or t0,t0,a3
> + and s0,t0,t4
> + li t1,-16711680
> + addi t1,t1,-1
> + or s0,s0,a4
> + and t0,s0,t1
> + or t0,t0,a5
> + and t0,t0,t2
> + or s0,t0,a6
> + sw s0,4(sp)
> + lw s0,8(sp)
> + slli a7,a7,16
> + li t0,65536
> + srli a7,a7,16
> + addi t0,t0,-1
> + sw s1,40(sp)
> + slli s1,t3,16
> + vsetvli t3,zero,e16,m1,ta,ma
> + sw s2,36(sp)
> + sw s3,32(sp)
> + andi s2,s0,-256
> + addi t3,sp,16
> + and s0,a7,t0
> + vmv.v.i v1,0
> + or s0,s0,s1
> + vs1r.v v1,0(t3)
> + sw s0,16(sp)
> + lw s0,20(sp)
> + li t3,-65536
> + or s2,s2,a3
> + and s0,t3,s0
> + and s3,s2,t4
> + or s0,s0,a7
> + or s3,s3,a4
> + and s0,s0,t0
> + and s2,s3,t1
> + or s0,s0,s1
> + or s2,s2,a5
> + sw s0,20(sp)
> + lw s0,12(sp)
> + and s2,s2,t2
> + or s2,s2,a6
> + sw s2,8(sp)
> + andi s2,s0,-256
> + lw s0,24(sp)
> + or s2,s2,a3
> + and t4,s2,t4
> + and s0,t3,s0
> + or a3,s0,a7
> + and a3,a3,t0
> + or t4,t4,a4
> + or a4,a3,s1
> + sw a4,24(sp)
> + lw a4,28(sp)
> + and t1,t4,t1
> + or t1,t1,a5
> + and t3,t3,a4
> + or t3,t3,a7
> + and t1,t1,t2
> + and t3,t3,t0
> + or a4,t1,a6
> + sw a4,12(sp)
> + or a4,t3,s1
> + slli a7,t5,2
> + sw a4,28(sp)
> + li a5,48
> + vsetvli a4,zero,e32,m1,ta,ma
> + mv t3,a7
> + vmv.v.x v1,t6
> + bltu a7,a5,.L14
> + li a5,32
> + addi t3,t3,-48
> + mv t4,a7
> + bltu a7,a5,.L15
> +.L5:
> + li a5,16
> + addi t4,t4,-32
> + mv t1,a7
> + bltu a7,a5,.L16
> +.L6:
> + addi t1,t1,-16
> +.L7:
> + vsetvli a6,a7,e8,m4,tu,mu
> + vl1re8.v v2,0(sp)
> + addi a4,a0,16
> + vsetvli zero,a6,e8,m1,ta,ma
> + vse8.v v2,0(a0)
> + addi a5,a0,32
> + vsetvli a3,t1,e8,m4,tu,mu
> + vsetvli zero,a3,e8,m1,ta,ma
> + vse8.v v2,0(a4)
> + addi t6,a0,48
> + vsetvli a4,t4,e8,m4,tu,mu
> + vsetvli zero,a4,e8,m1,ta,ma
> + vse8.v v2,0(a5)
> + srli t5,a6,1
> + vsetvli a5,t3,e8,m4,tu,mu
> + addi s0,sp,16
> + vsetvli zero,a5,e8,m1,ta,ma
> + vse8.v v2,0(t6)
> + vl1re16.v v2,0(s0)
> + srli t6,a3,1
> + vsetvli zero,t5,e16,m1,ta,ma
> + addi t5,a1,16
> + vse16.v v2,0(a1)
> + vsetvli zero,t6,e16,m1,ta,ma
> + srli t6,a4,1
> + vse16.v v2,0(t5)
> + addi t5,a1,32
> + vsetvli zero,t6,e16,m1,ta,ma
> + srli t6,a5,1
> + vse16.v v2,0(t5)
> + addi t5,a1,48
> + vsetvli zero,t6,e16,m1,ta,ma
> + vse16.v v2,0(t5)
> + srli t5,a6,2
> + vsetvli zero,t5,e32,m1,ta,ma
> + addi t6,a2,16
> + vse32.v v1,0(a2)
> + srli a3,a3,2
> + vsetvli zero,a3,e32,m1,ta,ma
> + addi t5,a2,32
> + vse32.v v1,0(t6)
> + srli a4,a4,2
> + addi a3,a2,48
> + vsetvli zero,a4,e32,m1,ta,ma
> + srli a5,a5,2
> + vse32.v v1,0(t5)
> + sub a7,a7,a6
> + vsetvli zero,a5,e32,m1,ta,ma
> + vse32.v v1,0(a3)
> + sub t1,t1,a6
> + sub t4,t4,a6
> + sub t3,t3,a6
> + addi a0,a0,64
> + addi a1,a1,64
> + addi a2,a2,64
> + bne a7,zero,.L7
> + lw s0,44(sp)
> + lw s1,40(sp)
> + lw s2,36(sp)
> + lw s3,32(sp)
> +.L1:
> + addi sp,sp,48
> + jr ra
> +.L16:
> + li t1,16
> + j .L6
> +.L15:
> + li t4,32
> + li a5,16
> + addi t4,t4,-32
> + mv t1,a7
> + bgeu a7,a5,.L6
> + j .L16
> +.L14:
> + li t3,48
> + li a5,32
> + addi t3,t3,-48
> + mv t4,a7
> + bgeu a7,a5,.L5
> + j .L15
> +.L3:
> + slli t5,t5,2
> + add t5,a0,t5
> +.L9:
> + sb a3,0(a0)
> + sb a4,1(a0)
> + sb a5,2(a0)
> + sb a6,3(a0)
> + sh a7,0(a1)
> + sh t3,2(a1)
> + sw t6,0(a2)
> + addi a0,a0,4
> + addi a1,a1,4
> + addi a2,a2,4
> + bne a0,t5,.L9
> + addi sp,sp,48
> + jr ra
> + .size test_1_TYPE1_int16_t, .-test_1_TYPE1_int16_t
> + .align 1
> + .globl test_1_TYPE1_uint16_t
> + .type test_1_TYPE1_uint16_t, @function
> +test_1_TYPE1_uint16_t:
> + addi sp,sp,-48
> + lw t1,56(sp)
> + lhu t4,48(sp)
> + lw t5,52(sp)
> + ble t1,zero,.L17
> + or t3,a2,a1
> + or t3,a0,t3
> + andi t3,t3,15
> + bne t3,zero,.L19
> + slli a4,a4,8
> + slli a5,a5,16
> + or t6,a3,a4
> + vsetvli t3,zero,e8,m1,ta,ma
> + li t2,16777216
> + addi t2,t2,-1
> + or t3,t6,a5
> + slli a6,a6,24
> + and t3,t3,t2
> + vmv.v.i v1,0
> + sw s0,44(sp)
> + vs1r.v v1,0(sp)
> + or s0,t3,a6
> + sw s0,0(sp)
> + lw s0,4(sp)
> + li t6,-65536
> + addi t6,t6,255
> + andi t0,s0,-256
> + or t0,t0,a3
> + and s0,t0,t6
> + li t3,-16711680
> + addi t3,t3,-1
> + or s0,s0,a4
> + and t0,s0,t3
> + or t0,t0,a5
> + and t0,t0,t2
> + or s0,t0,a6
> + sw s0,4(sp)
> + lw s0,8(sp)
> + li t0,65536
> + addi t0,t0,-1
> + sw s2,36(sp)
> + andi s2,s0,-256
> + slli s0,t4,16
> + vsetvli t4,zero,e16,m1,ta,ma
> + sw s1,40(sp)
> + sw s3,32(sp)
> + addi t4,sp,16
> + and s1,a7,t0
> + vmv.v.i v1,0
> + or s1,s1,s0
> + vs1r.v v1,0(t4)
> + sw s1,16(sp)
> + lw s1,20(sp)
> + li t4,-65536
> + or s2,s2,a3
> + and s1,t4,s1
> + and s3,s2,t6
> + or s1,s1,a7
> + or s3,s3,a4
> + and s1,s1,t0
> + and s2,s3,t3
> + or s1,s1,s0
> + or s2,s2,a5
> + sw s1,20(sp)
> + lw s1,12(sp)
> + and s2,s2,t2
> + or s2,s2,a6
> + sw s2,8(sp)
> + andi s2,s1,-256
> + lw s1,24(sp)
> + or s2,s2,a3
> + and t6,s2,t6
> + and s1,t4,s1
> + or a3,s1,a7
> + and a3,a3,t0
> + or t6,t6,a4
> + or a4,a3,s0
> + sw a4,24(sp)
> + lw a4,28(sp)
> + and t3,t6,t3
> + or t3,t3,a5
> + and t4,t4,a4
> + and t3,t3,t2
> + or t4,t4,a7
> + or a4,t3,a6
> + and t4,t4,t0
> + sw a4,12(sp)
> + or a4,t4,s0
> + slli t1,t1,2
> + sw a4,28(sp)
> + li a5,48
> + vsetvli a4,zero,e32,m1,ta,ma
> + mv t3,t1
> + vmv.v.x v1,t5
> + bltu t1,a5,.L29
> + li a5,32
> + addi t3,t3,-48
> + mv t4,t1
> + bltu t1,a5,.L30
> +.L21:
> + li a5,16
> + addi t4,t4,-32
> + mv a7,t1
> + bltu t1,a5,.L31
> +.L22:
> + addi a7,a7,-16
> +.L23:
> + vsetvli a6,t1,e8,m4,tu,mu
> + vl1re8.v v2,0(sp)
> + addi a4,a0,16
> + vsetvli zero,a6,e8,m1,ta,ma
> + vse8.v v2,0(a0)
> + addi a5,a0,32
> + vsetvli a3,a7,e8,m4,tu,mu
> + vsetvli zero,a3,e8,m1,ta,ma
> + vse8.v v2,0(a4)
> + addi t6,a0,48
> + vsetvli a4,t4,e8,m4,tu,mu
> + vsetvli zero,a4,e8,m1,ta,ma
> + vse8.v v2,0(a5)
> + srli t5,a6,1
> + vsetvli a5,t3,e8,m4,tu,mu
> + addi s0,sp,16
> + vsetvli zero,a5,e8,m1,ta,ma
> + vse8.v v2,0(t6)
> + vl1re16.v v2,0(s0)
> + srli t6,a3,1
> + vsetvli zero,t5,e16,m1,ta,ma
> + addi t5,a1,16
> + vse16.v v2,0(a1)
> + vsetvli zero,t6,e16,m1,ta,ma
> + srli t6,a4,1
> + vse16.v v2,0(t5)
> + addi t5,a1,32
> + vsetvli zero,t6,e16,m1,ta,ma
> + srli t6,a5,1
> + vse16.v v2,0(t5)
> + addi t5,a1,48
> + vsetvli zero,t6,e16,m1,ta,ma
> + vse16.v v2,0(t5)
> + srli t5,a6,2
> + vsetvli zero,t5,e32,m1,ta,ma
> + addi t6,a2,16
> + vse32.v v1,0(a2)
> + srli a3,a3,2
> + vsetvli zero,a3,e32,m1,ta,ma
> + addi t5,a2,32
> + vse32.v v1,0(t6)
> + srli a4,a4,2
> + addi a3,a2,48
> + vsetvli zero,a4,e32,m1,ta,ma
> + srli a5,a5,2
> + vse32.v v1,0(t5)
> + sub t1,t1,a6
> + vsetvli zero,a5,e32,m1,ta,ma
> + vse32.v v1,0(a3)
> + sub a7,a7,a6
> + sub t4,t4,a6
> + sub t3,t3,a6
> + addi a0,a0,64
> + addi a1,a1,64
> + addi a2,a2,64
> + bne t1,zero,.L23
> + lw s0,44(sp)
> + lw s1,40(sp)
> + lw s2,36(sp)
> + lw s3,32(sp)
> +.L17:
> + addi sp,sp,48
> + jr ra
> +.L31:
> + li a7,16
> + j .L22
> +.L30:
> + li t4,32
> + li a5,16
> + addi t4,t4,-32
> + mv a7,t1
> + bgeu t1,a5,.L22
> + j .L31
> +.L29:
> + li t3,48
> + li a5,32
> + addi t3,t3,-48
> + mv t4,t1
> + bgeu t1,a5,.L21
> + j .L30
> +.L19:
> + slli t1,t1,2
> + add t1,a0,t1
> +.L25:
> + sb a3,0(a0)
> + sb a4,1(a0)
> + sb a5,2(a0)
> + sb a6,3(a0)
> + sh a7,0(a1)
> + sh t4,2(a1)
> + sw t5,0(a2)
> + addi a0,a0,4
> + addi a1,a1,4
> + addi a2,a2,4
> + bne a0,t1,.L25
> + addi sp,sp,48
> + jr ra
> + .size test_1_TYPE1_uint16_t, .-test_1_TYPE1_uint16_t
> + .align 1
> + .globl test_1_TYPE1_int32_t
> + .type test_1_TYPE1_int32_t, @function
> +test_1_TYPE1_int32_t:
> + addi sp,sp,-64
> + lw t1,80(sp)
> + lw t3,64(sp)
> + lw t5,72(sp)
> + lw t6,76(sp)
> + ble t1,zero,.L32
> + addi t0,t1,-1
> + li t4,6
> + bleu t0,t4,.L34
> + or t4,a2,a1
> + or t4,a0,t4
> + andi t4,t4,15
> + beq t4,zero,.L44
> +.L34:
> + slli t1,t1,3
> + add t1,a0,t1
> +.L40:
> + sh a3,0(a0)
> + sh a4,2(a0)
> + sh a5,4(a0)
> + sh a6,6(a0)
> + sw a7,0(a1)
> + sw t3,4(a1)
> + sw t5,0(a2)
> + sw t6,4(a2)
> + addi a0,a0,8
> + addi a1,a1,8
> + addi a2,a2,8
> + bne a0,t1,.L40
> +.L32:
> + addi sp,sp,64
> + jr ra
> +.L44:
> + sw s0,60(sp)
> + slli t2,a3,16
> + li s0,65536
> + addi s0,s0,-1
> + vsetvli t4,zero,e16,m1,ta,ma
> + srli t2,t2,16
> + slli a4,a4,16
> + and a3,t2,s0
> + addi t4,sp,8
> + or a3,a3,a4
> + vmv.v.i v1,0
> + vs1r.v v1,0(t4)
> + sw a3,8(sp)
> + lw a3,12(sp)
> + li t4,-65536
> + slli a5,a5,16
> + and t0,t4,a3
> + srli a5,a5,16
> + or t0,t0,a5
> + slli a6,a6,16
> + and t0,t0,s0
> + or a3,t0,a6
> + sw a3,12(sp)
> + lw a3,16(sp)
> + sw t3,28(sp)
> + sw t3,36(sp)
> + and a3,t4,a3
> + or a3,a3,t2
> + and a3,a3,s0
> + or a4,a3,a4
> + sw a4,16(sp)
> + lw a4,20(sp)
> + sw a7,24(sp)
> + sw a7,32(sp)
> + and t4,t4,a4
> + or a5,t4,a5
> + and t4,a5,s0
> + or a4,t4,a6
> + sw a4,20(sp)
> + sw t5,40(sp)
> + sw t6,44(sp)
> + slli a5,t1,2
> + addi s0,sp,40
> + li a3,24
> + vsetvli a4,zero,e64,m1,ta,ma
> + mv t3,a5
> + vlse64.v v1,0(s0),zero
> + bltu a5,a3,.L45
> + li a4,16
> + addi t3,t3,-24
> + mv t4,a5
> + bltu a5,a4,.L46
> +.L36:
> + li a4,8
> + addi t4,t4,-16
> + mv t1,a5
> + bltu a5,a4,.L47
> +.L37:
> + addi t1,t1,-8
> +.L38:
> + addi a3,sp,8
> + vsetvli a4,a5,e8,m2,tu,mu
> + vl1re16.v v2,0(a3)
> + addi a6,a0,16
> + vsetvli zero,a4,e16,m1,ta,ma
> + vse16.v v2,0(a0)
> + addi a3,a0,32
> + vsetvli a7,t1,e8,m2,tu,mu
> + vsetvli zero,a7,e16,m1,ta,ma
> + vse16.v v2,0(a6)
> + addi t6,a0,48
> + vsetvli a6,t4,e8,m2,tu,mu
> + vsetvli zero,a6,e16,m1,ta,ma
> + vse16.v v2,0(a3)
> + srli t5,a4,1
> + vsetvli a3,t3,e8,m2,tu,mu
> + addi s0,sp,24
> + vsetvli zero,a3,e16,m1,ta,ma
> + vse16.v v2,0(t6)
> + vl1re32.v v2,0(s0)
> + srli t6,a7,1
> + vsetvli zero,t5,e32,m1,ta,ma
> + addi t5,a1,16
> + vse32.v v2,0(a1)
> + vsetvli zero,t6,e32,m1,ta,ma
> + srli t6,a6,1
> + vse32.v v2,0(t5)
> + addi t5,a1,32
> + vsetvli zero,t6,e32,m1,ta,ma
> + srli t6,a3,1
> + vse32.v v2,0(t5)
> + addi t5,a1,48
> + vsetvli zero,t6,e32,m1,ta,ma
> + vse32.v v2,0(t5)
> + srli t5,a4,2
> + vsetvli zero,t5,e64,m1,ta,ma
> + addi t6,a2,16
> + vse64.v v1,0(a2)
> + srli a7,a7,2
> + vsetvli zero,a7,e64,m1,ta,ma
> + addi t5,a2,32
> + vse64.v v1,0(t6)
> + srli a6,a6,2
> + addi a7,a2,48
> + vsetvli zero,a6,e64,m1,ta,ma
> + srli a3,a3,2
> + vse64.v v1,0(t5)
> + sub a5,a5,a4
> + vsetvli zero,a3,e64,m1,ta,ma
> + vse64.v v1,0(a7)
> + sub t1,t1,a4
> + sub t4,t4,a4
> + sub t3,t3,a4
> + addi a0,a0,64
> + addi a1,a1,64
> + addi a2,a2,64
> + bne a5,zero,.L38
> + lw s0,60(sp)
> + addi sp,sp,64
> + jr ra
> +.L47:
> + li t1,8
> + j .L37
> +.L46:
> + li t4,16
> + li a4,8
> + addi t4,t4,-16
> + mv t1,a5
> + bgeu a5,a4,.L37
> + j .L47
> +.L45:
> + li t3,24
> + li a4,16
> + addi t3,t3,-24
> + mv t4,a5
> + bgeu a5,a4,.L36
> + j .L46
> + .size test_1_TYPE1_int32_t, .-test_1_TYPE1_int32_t
> + .align 1
> + .globl test_1_TYPE1_uint32_t
> + .type test_1_TYPE1_uint32_t, @function
> +test_1_TYPE1_uint32_t:
> + addi sp,sp,-48
> + lw t1,64(sp)
> + lw t5,48(sp)
> + lw t3,56(sp)
> + lw t4,60(sp)
> + ble t1,zero,.L48
> + addi t0,t1,-1
> + li t6,6
> + bleu t0,t6,.L50
> + or t6,a2,a1
> + or t6,a0,t6
> + andi t6,t6,15
> + beq t6,zero,.L60
> +.L50:
> + slli t1,t1,3
> + add t1,a0,t1
> +.L56:
> + sh a3,0(a0)
> + sh a4,2(a0)
> + sh a5,4(a0)
> + sh a6,6(a0)
> + sw a7,0(a1)
> + sw t5,4(a1)
> + sw t3,0(a2)
> + sw t4,4(a2)
> + addi a0,a0,8
> + addi a1,a1,8
> + addi a2,a2,8
> + bne a0,t1,.L56
> +.L48:
> + addi sp,sp,48
> + jr ra
> +.L60:
> + li t0,65536
> + addi t0,t0,-1
> + vsetvli t6,zero,e16,m1,ta,ma
> + slli a4,a4,16
> + and t2,a3,t0
> + addi t6,sp,8
> + or t2,t2,a4
> + vmv.v.i v1,0
> + vs1r.v v1,0(t6)
> + sw t2,8(sp)
> + lw t2,12(sp)
> + li t6,-65536
> + slli a6,a6,16
> + and t2,t6,t2
> + or t2,t2,a5
> + and t2,t2,t0
> + or t2,t2,a6
> + sw t2,12(sp)
> + lw t2,16(sp)
> + sw t3,40(sp)
> + sw a7,24(sp)
> + and t2,t6,t2
> + or a3,t2,a3
> + and a3,a3,t0
> + or a4,a3,a4
> + sw a4,16(sp)
> + lw a4,20(sp)
> + sw t5,28(sp)
> + sw a7,32(sp)
> + and t6,t6,a4
> + or t6,t6,a5
> + and t6,t6,t0
> + or a5,t6,a6
> + sw a5,20(sp)
> + sw t4,44(sp)
> + slli a4,t1,2
> + sw t5,36(sp)
> + addi a6,sp,40
> + li a3,24
> + vsetvli a5,zero,e64,m1,ta,ma
> + mv t3,a4
> + vlse64.v v1,0(a6),zero
> + bltu a4,a3,.L61
> + li a5,16
> + addi t3,t3,-24
> + mv t4,a4
> + bltu a4,a5,.L62
> +.L52:
> + li a5,8
> + addi t4,t4,-16
> + mv t1,a4
> + bltu a4,a5,.L63
> +.L53:
> + addi t1,t1,-8
> +.L54:
> + addi a3,sp,8
> + vsetvli a5,a4,e8,m2,tu,mu
> + vl1re16.v v2,0(a3)
> + addi a6,a0,16
> + vsetvli zero,a5,e16,m1,ta,ma
> + vse16.v v2,0(a0)
> + addi a3,a0,32
> + vsetvli a7,t1,e8,m2,tu,mu
> + vsetvli zero,a7,e16,m1,ta,ma
> + vse16.v v2,0(a6)
> + addi t6,a0,48
> + vsetvli a6,t4,e8,m2,tu,mu
> + vsetvli zero,a6,e16,m1,ta,ma
> + vse16.v v2,0(a3)
> + srli t5,a5,1
> + vsetvli a3,t3,e8,m2,tu,mu
> + vsetvli zero,a3,e16,m1,ta,ma
> + vse16.v v2,0(t6)
> + addi t6,sp,24
> + vl1re32.v v2,0(t6)
> + vsetvli zero,t5,e32,m1,ta,ma
> + srli t6,a7,1
> + vse32.v v2,0(a1)
> + addi t5,a1,16
> + vsetvli zero,t6,e32,m1,ta,ma
> + srli t6,a6,1
> + vse32.v v2,0(t5)
> + addi t5,a1,32
> + vsetvli zero,t6,e32,m1,ta,ma
> + srli t6,a3,1
> + vse32.v v2,0(t5)
> + addi t5,a1,48
> + vsetvli zero,t6,e32,m1,ta,ma
> + vse32.v v2,0(t5)
> + srli t5,a5,2
> + vsetvli zero,t5,e64,m1,ta,ma
> + addi t6,a2,16
> + vse64.v v1,0(a2)
> + srli a7,a7,2
> + vsetvli zero,a7,e64,m1,ta,ma
> + addi t5,a2,32
> + vse64.v v1,0(t6)
> + srli a6,a6,2
> + addi a7,a2,48
> + vsetvli zero,a6,e64,m1,ta,ma
> + srli a3,a3,2
> + vse64.v v1,0(t5)
> + sub a4,a4,a5
> + vsetvli zero,a3,e64,m1,ta,ma
> + vse64.v v1,0(a7)
> + sub t1,t1,a5
> + sub t4,t4,a5
> + sub t3,t3,a5
> + addi a0,a0,64
> + addi a1,a1,64
> + addi a2,a2,64
> + bne a4,zero,.L54
> + addi sp,sp,48
> + jr ra
> +.L63:
> + li t1,8
> + j .L53
> +.L62:
> + li t4,16
> + li a5,8
> + addi t4,t4,-16
> + mv t1,a4
> + bgeu a4,a5,.L53
> + j .L63
> +.L61:
> + li t3,24
> + li a5,16
> + addi t3,t3,-24
> + mv t4,a4
> + bgeu a4,a5,.L52
> + j .L62
> + .size test_1_TYPE1_uint32_t, .-test_1_TYPE1_uint32_t
> + .ident "GCC: (GNU) 13.0.1 20230324 (experimental)"
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
> new file mode 100644
> index 00000000000..d3e187eae68
> --- /dev/null
> +++
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
> @@ -0,0 +1,19 @@
> +/* { dg-do run { target { riscv_vector } } } */
> +/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" }
> */
> +
> +#include "multiple_rgroup-1.c"
> +
> +int main (void)
> +{
> + TEST_ALL (run_1)
> + TEST_ALL (run_2)
> + TEST_ALL (run_3)
> + TEST_ALL (run_4)
> + TEST_ALL (run_5)
> + TEST_ALL (run_6)
> + TEST_ALL (run_7)
> + TEST_ALL (run_8)
> + TEST_ALL (run_9)
> + TEST_ALL (run_10)
> + return 0;
> +}
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
> new file mode 100644
> index 00000000000..5166c9e35a0
> --- /dev/null
> +++
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
> @@ -0,0 +1,19 @@
> +/* { dg-do run { target { riscv_vector } } } */
> +/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" }
> */
> +
> +#include "multiple_rgroup-2.c"
> +
> +int main (void)
> +{
> + TEST_ALL (run_1)
> + TEST_ALL (run_2)
> + TEST_ALL (run_3)
> + TEST_ALL (run_4)
> + TEST_ALL (run_5)
> + TEST_ALL (run_6)
> + TEST_ALL (run_7)
> + TEST_ALL (run_8)
> + TEST_ALL (run_9)
> + TEST_ALL (run_10)
> + return 0;
> +}
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
> new file mode 100644
> index 00000000000..6384888dd03
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param
> riscv-autovec-preference=scalable -fno-vect-cost-model
> -fno-tree-loop-distribute-patterns" } */
> +
> +#include "single_rgroup-1.h"
> +
> +TEST_ALL (test_1)
> +
> +/* { dg-final { scan-assembler-times {vsetvli} 10 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> new file mode 100644
> index 00000000000..be6b4c641cb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
> @@ -0,0 +1,106 @@
> +#include <stddef.h>
> +#include <stdint.h>
> +
> +#define N 777
> +
> +#define test_1(TYPE)
> \
> + TYPE a_##TYPE[N];
> \
> + TYPE b_##TYPE[N];
> \
> + void __attribute__ ((noinline, noclone)) test_1_##TYPE (unsigned int n)
> \
> + {
> \
> + unsigned int i = 0;
> \
> + for (i = 0; i < n; i++)
> \
> + b_##TYPE[i] = a_##TYPE[i];
> \
> + }
> +
> +#define run_1(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 33 + 1 + 109;
> \
> + test_1_##TYPE (5);
> \
> + for (unsigned int i = 0; i < 5; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_2(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 57 + 1 + 999;
> \
> + test_1_##TYPE (17);
> \
> + for (unsigned int i = 0; i < 17; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_3(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 77 + 1 + 3;
> \
> + test_1_##TYPE (32);
> \
> + for (unsigned int i = 0; i < 32; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_4(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 45 + 1 + 11;
> \
> + test_1_##TYPE (128);
> \
> + for (unsigned int i = 0; i < 128; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_5(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 199 + 1 + 79;
> \
> + test_1_##TYPE (177);
> \
> + for (unsigned int i = 0; i < 177; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_6(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 377 + 1 + 73;
> \
> + test_1_##TYPE (255);
> \
> + for (unsigned int i = 0; i < 255; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_7(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 98 + 1 + 66;
> \
> + test_1_##TYPE (333);
> \
> + for (unsigned int i = 0; i < 333; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_8(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 7 + 1 * 7;
> \
> + test_1_##TYPE (512);
> \
> + for (unsigned int i = 0; i < 512; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_9(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 + 1 + 88;
> \
> + test_1_##TYPE (637);
> \
> + for (unsigned int i = 0; i < 637; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define run_10(TYPE)
> \
> + for (unsigned int i = 0; i < N; i++)
> \
> + a_##TYPE[i] = i * 2 * 331 + 1 + 547;
> \
> + test_1_##TYPE (777);
> \
> + for (unsigned int i = 0; i < 777; i++)
> \
> + if (b_##TYPE[i] != a_##TYPE[i])
> \
> + __builtin_abort ();
> +
> +#define TEST_ALL(T)
> \
> + T (int8_t)
> \
> + T (uint8_t)
> \
> + T (int16_t)
> \
> + T (uint16_t)
> \
> + T (int32_t)
> \
> + T (uint32_t)
> \
> + T (int64_t)
> \
> + T (uint64_t)
> \
> + T (float)
> \
> + T (double)
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
> new file mode 100644
> index 00000000000..4af2f18de8a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
> @@ -0,0 +1,19 @@
> +/* { dg-do run { target { riscv_vector } } } */
> +/* { dg-additional-options "-fno-vect-cost-model
> -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable"
> } */
> +
> +#include "single_rgroup-1.c"
> +
> +int main (void)
> +{
> + TEST_ALL (run_1)
> + TEST_ALL (run_2)
> + TEST_ALL (run_3)
> + TEST_ALL (run_4)
> + TEST_ALL (run_5)
> + TEST_ALL (run_6)
> + TEST_ALL (run_7)
> + TEST_ALL (run_8)
> + TEST_ALL (run_9)
> + TEST_ALL (run_10)
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h
> new file mode 100644
> index 00000000000..799e2d7d754
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h
> @@ -0,0 +1,68 @@
> +#include <stddef.h>
> +#include <stdint.h>
> +
> +void
> +foo0 (int8_t *__restrict f, int16_t *__restrict d, int n)
> +{
> + for (int i = 0; i < n; ++i)
> + {
> + f[i * 2 + 0] = 1;
> + f[i * 2 + 1] = 2;
> + d[i] = 3;
> + }
> +}
> +
> +void
> +foo1 (int16_t *__restrict f, int32_t *__restrict d, int n)
> +{
> + for (int i = 0; i < n; ++i)
> + {
> + f[i * 2 + 0] = 1;
> + f[i * 2 + 1] = 2;
> + d[i] = 3;
> + }
> +}
> +
> +void
> +foo2 (int32_t *__restrict f, int64_t *__restrict d, int n)
> +{
> + for (int i = 0; i < n; ++i)
> + {
> + f[i * 2 + 0] = 1;
> + f[i * 2 + 1] = 2;
> + d[i] = 3;
> + }
> +}
> +
> +void
> +foo3 (int16_t *__restrict f, float *__restrict d, int n)
> +{
> + for (int i = 0; i < n; ++i)
> + {
> + f[i * 2 + 0] = 1;
> + f[i * 2 + 1] = 2;
> + d[i] = 3;
> + }
> +}
> +
> +void
> +foo4 (int32_t *__restrict f, float *__restrict d, int n)
> +{
> + for (int i = 0; i < n; ++i)
> + {
> + f[i * 2 + 0] = 1;
> + f[i * 2 + 1] = 2;
> + d[i] = 3;
> + }
> +}
> +
> +void
> +foo5 (float *__restrict f, double *__restrict d, int n)
> +{
> + for (int i = 0; i < n; ++i)
> + {
> + f[i * 2 + 0] = 1;
> + f[i * 2 + 1] = 2;
> + d[i] = 3;
> + }
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
> new file mode 100644
> index 00000000000..7ff84f60749
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
> new file mode 100644
> index 00000000000..dc22eefbd36
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
> new file mode 100644
> index 00000000000..36f6d98a5cb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
> new file mode 100644
> index 00000000000..794f28e73bd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
> new file mode 100644
> index 00000000000..d5e36190b31
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
> new file mode 100644
> index 00000000000..d154df4c4ba
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fno-vect-cost-model -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
> new file mode 100644
> index 00000000000..68e7696ed65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
> new file mode 100644
> index 00000000000..f8860a36332
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> +
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
> new file mode 100644
> index 00000000000..3a6a3aa1261
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
> new file mode 100644
> index 00000000000..d1aaf3f4297
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
> new file mode 100644
> index 00000000000..0d03536389f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
> new file mode 100644
> index 00000000000..ca423285011
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
> new file mode 100644
> index 00000000000..4c6c7e2fb3b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
> new file mode 100644
> index 00000000000..b8253476973
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
> new file mode 100644
> index 00000000000..e7900b82215
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
> new file mode 100644
> index 00000000000..1c0e8c2785b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
> new file mode 100644
> index 00000000000..daf4a4e8e64
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
> new file mode 100644
> index 00000000000..3866e45546c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
> new file mode 100644
> index 00000000000..4c190c303c1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
> new file mode 100644
> index 00000000000..66bb1f44170
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
> new file mode 100644
> index 00000000000..6920a395d1c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
> @@ -0,0 +1,4 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=scalable -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
> new file mode 100644
> index 00000000000..d8b60babf9a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param
> riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize
> -fdump-tree-vect-details -save-temps" } */
> +
> +#include "template-1.h"
> +
> +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3
> "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 7a9a2b6ac48..5893dbf9742 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -44,6 +44,22 @@ dg-runtest [lsort [glob -nocomplain
> $srcdir/$subdir/base/*.\[cS\]]] \
> "" $CFLAGS
> gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
> "" $CFLAGS
> +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
> + "" $CFLAGS
> +
> +set AUTOVEC_TEST_OPTS [list \
> + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \
> + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \
> + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \
> + {-ftree-vectorize -O3 --param riscv-autovec-lmul=m8} \
> + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \
> + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \
> + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} \
> + {-ftree-vectorize -O2 --param riscv-autovec-lmul=m8} ]
> +foreach op $AUTOVEC_TEST_OPTS {
> + gcc-dg-runtest [lsort [glob -nocomplain
> $srcdir/$subdir/autovec/partial/*.\[cS\]]] \
> + "" "$op"
> +}
>
> # All done.
> dg-finish
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
> index ee58f9bbdfc..8a1bbb40fc8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
> @@ -11,4 +11,4 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t
> *out, size_t n, int c
> __riscv_vse32_v_i32m1(out, c, __riscv_vsetvl_e8mf2 (vl));
> }
>
> -/* { dg-final { scan-assembler-times {vsetvli} 8 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> \ No newline at end of file
> +/* { dg-final { scan-assembler-times {vsetvli} 7 { target { no-opts "-O0"
> no-opts "-g" no-opts "-funroll-loops" } } } } */
> --
> 2.36.3
>
