These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-10 Patrick O'Neill <patr...@rivosinc.com>
* amo-table-a-6-amo-add-1.c: New test.
* amo-table-a-6-amo-add-2.c: Likewise.
* amo-table-a-6-amo-add-3.c: Likewise.
* amo-table-a-6-amo-add-4.c: Likewise.
* amo-table-a-6-amo-add-5.c: Likewise.
* amo-table-a-6-compare-exchange-1.c: Likewise.
* amo-table-a-6-compare-exchange-2.c: Likewise.
* amo-table-a-6-compare-exchange-3.c: Likewise.
* amo-table-a-6-compare-exchange-4.c: Likewise.
* amo-table-a-6-compare-exchange-5.c: Likewise.
* amo-table-a-6-fence-1.c: Likewise.
* amo-table-a-6-fence-2.c: Likewise.
* amo-table-a-6-fence-3.c: Likewise.
* amo-table-a-6-fence-4.c: Likewise.
* amo-table-a-6-fence-5.c: Likewise.
* amo-table-a-6-load-1.c: Likewise.
* amo-table-a-6-load-2.c: Likewise.
* amo-table-a-6-load-3.c: Likewise.
* amo-table-a-6-store-1.c: Likewise.
* amo-table-a-6-store-2.c: Likewise.
* amo-table-a-6-store-compat-3.c: Likewise.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
v3 Changelog:
* Consolidate existing tests in this patch
* Add new tests for store/load/amoadd
---
.../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 8 ++++++++
.../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 8 ++++++++
.../riscv/amo-table-a-6-compare-exchange-1.c | 12 ++++++++++++
.../riscv/amo-table-a-6-compare-exchange-2.c | 12 ++++++++++++
.../riscv/amo-table-a-6-compare-exchange-3.c | 12 ++++++++++++
.../riscv/amo-table-a-6-compare-exchange-4.c | 12 ++++++++++++
.../riscv/amo-table-a-6-compare-exchange-5.c | 12 ++++++++++++
.../gcc.target/riscv/amo-table-a-6-fence-1.c | 9 +++++++++
.../gcc.target/riscv/amo-table-a-6-fence-2.c | 7 +++++++
.../gcc.target/riscv/amo-table-a-6-fence-3.c | 7 +++++++
.../gcc.target/riscv/amo-table-a-6-fence-4.c | 7 +++++++
.../gcc.target/riscv/amo-table-a-6-fence-5.c | 7 +++++++
.../gcc.target/riscv/amo-table-a-6-load-1.c | 9 +++++++++
.../gcc.target/riscv/amo-table-a-6-load-2.c | 10 ++++++++++
.../gcc.target/riscv/amo-table-a-6-load-3.c | 10 ++++++++++
.../gcc.target/riscv/amo-table-a-6-store-1.c | 9 +++++++++
.../gcc.target/riscv/amo-table-a-6-store-2.c | 10 ++++++++++
.../gcc.target/riscv/amo-table-a-6-store-compat-3.c | 10 ++++++++++
21 files changed, 195 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
new file mode 100644
index 00000000000..ae7e407befc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
new file mode 100644
index 00000000000..60d84f32481
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
new file mode 100644
index 00000000000..a97231e4e73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
new file mode 100644
index 00000000000..3c843afdd5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
new file mode 100644
index 00000000000..3434229f5e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
new file mode 100644
index 00000000000..d96bc15e23b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler-not "lr.w.aq" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+/* { dg-final { scan-assembler-not "sc.w.rl" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED,
__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
new file mode 100644
index 00000000000..5d173641459
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler "lr.w.aq" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+/* { dg-final { scan-assembler-not "sc.w.rl" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME,
__ATOMIC_CONSUME);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
new file mode 100644
index 00000000000..36201027ab9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler "lr.w.aq" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+/* { dg-final { scan-assembler-not "sc.w.rl" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE,
__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
new file mode 100644
index 00000000000..3711bf7ddec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler "lr.w.aqrl" } } */
+/* { dg-final { scan-assembler "sc.w.rl" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST,
__ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
new file mode 100644
index 00000000000..fb0075a1a33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* Verify that compare exchange mappings match Table A.6's recommended
mapping. */
+/* { dg-final { scan-assembler "lr.w.aq" } } */
+/* { dg-final { scan-assembler "sc.w.rl" } } */
+/* { dg-final { scan-assembler-not "lr.w.rl" } } */
+/* { dg-final { scan-assembler-not "sc.w.aq" } } */
+
+void
+foo (int bar, int baz, int qux)
+{
+ __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE,
__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
new file mode 100644
index 00000000000..827a0f6781b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
new file mode 100644
index 00000000000..2d14a5b9681
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "fence\tr,rw" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
new file mode 100644
index 00000000000..c215dc19c90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "fence\trw,w" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
new file mode 100644
index 00000000000..6dec57593f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "fence.tso" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
new file mode 100644
index 00000000000..f05a33b1bcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "fence\trw,rw" } } */
+
+int main() {
+ __atomic_thread_fence(__ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
new file mode 100644
index 00000000000..8278198072e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
new file mode 100644
index 00000000000..faef2ce25c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "fence\tr,rw" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
new file mode 100644
index 00000000000..9210fd10a53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "fence\tr,rw" } } */
+/* { dg-final { scan-assembler "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
new file mode 100644
index 00000000000..e2fb71b17c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* Verify that load mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
new file mode 100644
index 00000000000..adaace33b30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that fence mappings match Table A.6's recommended mapping. */
+/* { dg-final { scan-assembler "fence\trw,w" } } */
+/* { dg-final { scan-assembler-not "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
new file mode 100644
index 00000000000..1fff6ce2857
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* Verify that store mapping are compatible with Table A.6 & A.7. */
+/* { dg-final { scan-assembler "fence\trw,w" } } */
+/* { dg-final { scan-assembler "fence\trw,rw" } } */
+/* { dg-final { scan-assembler-not "fence.tso" } } */
+
+void
+foo (int* bar, int* baz) {
+ __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
--
2.25.1
