Since vms<cmp> pattern has one more tail policy + avl_type operand,
wheras pred_mov<mode> (vmset.m/vmclr.m) only has avl_type operand.
GCC recognize (lt:(reg v) (reg v)) and lower it into (const_vector:0),
then map into pred_mov pattern (when both pred_mov and vms<cmp> pattern has
tail policy + avl_type operand).
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-19 17:34
To: Li, Pan2
CC: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Hi Pan:
> rtx expand (function_expander &e) const override diff --git
> a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index
> 0ecca98f20c..6819363b9ff 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred_mov<mode>"
> [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1,
> Wc1, Wc1, Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK,
> rK, rK, rK")
> (match_operand 5 "const_int_operand" " i, i,
> i, i, i")
> + (match_operand 6 "const_int_operand" " i, i,
> i, i, i")
I didn't get why having one more tail policy operand for this pattern
could help?
Do you mind explaining more detail about this?
Thanks :)
