On Wed, Apr 19, 2023 at 6:38 PM <juzhe.zh...@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
>
> This patch is adding 2 compile option for RVV auto-vectorization.
> 1. -param=riscv-autovec-preference=
> This option is to specify the auto-vectorization approach for RVV.
> Currently, we only support scalable and fixed-vlmax.
>
> - scalable means VLA auto-vectorization. The vector-length to compiler is
> unknown and runtime invariant. Such approach can allow us compile the
> code
> run on any vector-length RVV CPU.
>
> - fixed-vlmax means the compile known the RVV CPU vector-length, compile
> option
> in fixed-length VLS auto-vectorization. Meaning if we specify
> vector-length=512.
> The execution file can only run on vector-length = 512 RVV CPU.
>
> - TODO: we may need to support min-length VLS auto-vectorization, means
> the execution
> file can run on larger length RVV CPU.
Just as a generic comment - if the option should be exposed to users
rather than just used
for testsuite or development purposes it should eventually become a
-mautovec-preference=
flag (no need to prefix with riscv).
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add
> enum for auto-vectorization preference.
> (enum riscv_autovec_lmul_enum): Add enum for choosing LMUL of RVV
> auto-vectorization.
> * config/riscv/riscv.opt: Add compile option for RVV
> auto-vectorization.
>
> ---
> gcc/config/riscv/riscv-opts.h | 15 ++++++++++++++
> gcc/config/riscv/riscv.opt | 37 +++++++++++++++++++++++++++++++++++
> 2 files changed, 52 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index cf0cd669be4..4207db240ea 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -67,6 +67,21 @@ enum stack_protector_guard {
> SSP_GLOBAL /* global canary */
> };
>
> +/* RISC-V auto-vectorization preference. */
> +enum riscv_autovec_preference_enum {
> + NO_AUTOVEC,
> + RVV_SCALABLE,
> + RVV_FIXED_VLMAX
> +};
> +
> +/* RISC-V auto-vectorization RVV LMUL. */
> +enum riscv_autovec_lmul_enum {
> + RVV_M1 = 1,
> + RVV_M2 = 2,
> + RVV_M4 = 4,
> + RVV_M8 = 8
> +};
> +
> #define MASK_ZICSR (1 << 0)
> #define MASK_ZIFENCEI (1 << 1)
>
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index ff1dd4ddd4f..ef1bdfcfe28 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -254,3 +254,40 @@ Enum(isa_spec_class) String(20191213)
> Value(ISA_SPEC_CLASS_20191213)
> misa-spec=
> Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec)
> Init(TARGET_DEFAULT_ISA_SPEC)
> Set the version of RISC-V ISA spec.
> +
> +Enum
> +Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)
> +The RISC-V auto-vectorization preference:
> +
> +EnumValue
> +Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)
> +
> +EnumValue
> +Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)
> +
> +EnumValue
> +Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)
> +
> +-param=riscv-autovec-preference=
> +Target RejectNegative Joined Enum(riscv_autovec_preference)
> Var(riscv_autovec_preference) Init(NO_AUTOVEC)
> +-param=riscv-autovec-preference=<string> Set the preference of
> auto-vectorization in the RISC-V port.
> +
> +Enum
> +Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum)
> +The RVV possible LMUL:
> +
> +EnumValue
> +Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1)
> +
> +EnumValue
> +Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2)
> +
> +EnumValue
> +Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4)
> +
> +EnumValue
> +Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8)
> +
> +-param=riscv-autovec-lmul=
> +Target RejectNegative Joined Enum(riscv_autovec_lmul)
> Var(riscv_autovec_lmul) Init(RVV_M1)
> +-param=riscv-autovec-lmul=<string> Set the RVV LMUL of
> auto-vectorization in the RISC-V port.
> --
> 2.36.3
>
