On 3/27/23 19:01, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong <juzhe.zh...@rivai.ai>
void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
{
vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
for (int i = 0; i < n; i++){
v = __riscv_vor_vx_i8mf4 (v, 101, 32);
v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
}
__riscv_vse8_v_i8mf4 (out, v, 32);
}
before this patch:
f:
li a5,32
vsetvli zero,a5,e8,mf4,tu,ma
vle8.v v1,0(a0)
ble a3,zero,.L2
li t0,0
li a0,101
.L3:
addiw t0,t0,1
vor.vx v1,v1,a0
vle8.v v1,0(a1)
bne a3,t0,.L3
.L2:
vsetvli zero,zero,e8,mf4,tu,ma
vse8.v v1,0(a2)
ret
afther this patch:
f:
li a5,32
vsetvli zero,a5,e8,mf4,tu,ma
vle8.v v1,0(a0)
ble a3,zero,.L2
li t0,0
li a0,101
.L3:
addiw t0,t0,1
vor.vx v1,v1,a0
vle8.v v1,0(a1)
bne a3,t0,.L3
.L2:
vse8.v v1,0(a2)
ret
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::all_avail_in_compatible_p): New function.
(pass_vsetvl::refine_vsetvls): Remove redundant vsetvli.
* config/riscv/riscv-vsetvl.h: New function declare.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-102.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 67 ++++++++++++++++++-
gcc/config/riscv/riscv-vsetvl.h | 1 +
.../riscv/rvv/vsetvl/avl_single-102.c | 16 +++++
3 files changed, 81 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 4948e5d4c5e..58568b45010 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2376,6 +2376,23 @@ vector_infos_manager::all_empty_predecessor_p (const
basic_block cfg_bb) const
return true;
}
+bool
+vector_infos_manager::all_avail_in_compatible_p (const basic_block cfg_bb)
const
This needs a function comment. Perhaps:
/* Return TRUE if the incoming vector configuration state
to CFG_BB is compatible with the vector configuration
state in CFG_BB, FALSE otherwise. */
+
+ /* Optimize such case:
+ void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
+ {
+ vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+ for (int i = 0; i < n; i++){
+ v = __riscv_vor_vx_i8mf4 (v, 101, 32);
+ v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+ }
+ __riscv_vse8_v_i8mf4 (out, v, 32);
+ }
In general I would suggest rather than writing code like this in the
comments, instead describe the properties you're looking for. That way
someone who may not be a RISC-V expert can more easily interpret the
scenario you're looking for and what action you want to take when the
scenario is discovered.
In this particular case it look like you're trying to describe the
scenario where all incoming edges to a block have a vector state that is
compatbile with the block. In such a case we need not emit a vsetvl in
the current block.
THe right place for code is in the testsuite.
So generally OK, though you do need to adjust the comments slightly.
Please do that and repost for a final review/ACK.
Thanks,
Jeff
