From: Yanzhang Wang <yanzhang.w...@intel.com> PR 109617
gcc/ChangeLog: * config/riscv/vector-iterators.md: gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test. Signed-off-by: Yanzhang Wang <yanzhang.w...@intel.com> Co-authored-by: Pan Li <pan2...@intel.com> --- gcc/config/riscv/vector-iterators.md | 3 ++- .../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a8e856161d3..033659930d1 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -189,6 +189,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -220,7 +221,7 @@ (define_mode_iterator VLMULEXT32 [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128") - (VNx1HI "TARGET_MIN_VLEN < 128") + (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VLMULEXT64 [ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c new file mode 100644 index 00000000000..501d98c5897 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include <riscv_vector.h> + +vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { + return __riscv_vlmul_ext_v_i16mf4_i16m8(op1); +} + +vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { + return __riscv_vlmul_ext_v_i64m2_i64m8(op1); +} + +/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */ -- 2.39.2