LGTM, pushed to trunk > This patch try to legitimise the const0_rtx (aka zero register) > as the base register for the RVV load/store instructions. > > For example: > vint32m1_t test_vle32_v_i32m1_shortcut (size_t vl) > { > return __riscv_vle32_v_i32m1 ((int32_t *)0, vl); > }
The example is kind of counter intuitive to me, I know it's legal from ISA spec level, but can't understand why it's useful...until I saw you mention auto vec and index load - I realized this is optimization for gather/scatter code gen.