[PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv.

[Michael Collison]

From: Kevin Lee <kev...@rivosinc.com>

Kevin Lee <kev...@rivosinc.com>
gcc/ChangeLog:

        * tree-vect-data-refs.cc (vect_grouped_store_supported): Add new
condition
---
 gcc/tree-vect-data-refs.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/tree-vect-data-refs.cc b/gcc/tree-vect-data-refs.cc
index 8daf7bd7dd3..df393ba723d 100644
--- a/gcc/tree-vect-data-refs.cc
+++ b/gcc/tree-vect-data-refs.cc
@@ -5399,6 +5399,8 @@ vect_grouped_store_supported (tree vectype, unsigned 
HOST_WIDE_INT count)
          poly_uint64 nelt = GET_MODE_NUNITS (mode);
 
          /* The encoding has 2 interleaved stepped patterns.  */
+    if(!multiple_p (nelt, 2))
+      return false;
          vec_perm_builder sel (nelt, 2, 3);
          sel.quick_grow (6);
          for (i = 0; i < 3; i++)
-- 
2.34.1