Damm, I mixed something up else..
On Thu, Apr 27, 2023 at 4:53 PM Kito Cheng via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > `vr`, `vm` and `vd` constarint for vector register constarint, those 3 > constarint has implemented on LLVM as well. > > gcc/ChangeLog: > > * doc/md.texi (RISC-V): Add vr, vm, vd constarint. > --- > gcc/config/riscv/riscv-modes.def | 4 ++++ > gcc/config/riscv/riscv-protos.h | 2 ++ > gcc/config/riscv/riscv-selftests.cc | 16 +++++++++++++--- > gcc/config/riscv/riscv-v.cc | 12 ++++++++++++ > gcc/config/riscv/riscv.cc | 2 ++ > gcc/config/riscv/riscv.md | 1 + > gcc/doc/md.texi | 9 +++++++++ > 7 files changed, 43 insertions(+), 3 deletions(-) > > diff --git a/gcc/config/riscv/riscv-modes.def > b/gcc/config/riscv/riscv-modes.def > index b1669609eec4..4f9e5ed5f3e9 100644 > --- a/gcc/config/riscv/riscv-modes.def > +++ b/gcc/config/riscv/riscv-modes.def > @@ -185,6 +185,10 @@ VECTOR_MODE_WITH_PREFIX (VNx, INT, QI, 1, 0); > ADJUST_NUNITS (VNx1QI, riscv_v_adjust_nunits (VNx1QImode, 1)); > ADJUST_ALIGNMENT (VNx1QI, 1); > > + > +/* VLS modes. */ > +VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ > + > /* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can > be 65536 for a single vector register which means the vector mode in > GCC can be maximum = 65536 * 8 bits (LMUL=8). > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index 607ff6ea697b..28d9e4f5bb82 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -207,6 +207,8 @@ enum vlen_enum > bool slide1_sew64_helper (int, machine_mode, machine_mode, > machine_mode, rtx *); > rtx gen_avl_for_scalar_move (rtx); > +machine_mode minimal_vls_mode (machine_mode); > +machine_mode mask_mode(machine_mode); > } > > /* We classify builtin types into two classes: > diff --git a/gcc/config/riscv/riscv-selftests.cc > b/gcc/config/riscv/riscv-selftests.cc > index 1bf1a648fa1f..56c1260a64b1 100644 > --- a/gcc/config/riscv/riscv-selftests.cc > +++ b/gcc/config/riscv/riscv-selftests.cc > @@ -234,6 +234,16 @@ run_poly_int_selftests (void) > worklist); > } > > +static bool > +vls_mode_p (machine_mode mode) > +{ > + if (!riscv_v_ext_vector_mode_p(mode)) > + return false; > + poly_int64 sz = GET_MODE_SIZE (mode); > + return sz.is_constant(); > +} > + > + > static void > run_const_vector_selftests (void) > { > @@ -248,7 +258,7 @@ run_const_vector_selftests (void) > > FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT) > { > - if (riscv_v_ext_vector_mode_p (mode)) > + if (riscv_v_ext_vector_mode_p (mode) && !vls_mode_p (mode)) > { > for (const HOST_WIDE_INT &val : worklist) > { > @@ -273,7 +283,7 @@ run_const_vector_selftests (void) > > FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FLOAT) > { > - if (riscv_v_ext_vector_mode_p (mode)) > + if (riscv_v_ext_vector_mode_p (mode) && !vls_mode_p (mode)) > { > scalar_mode inner_mode = GET_MODE_INNER (mode); > REAL_VALUE_TYPE f = REAL_VALUE_ATOF ("0.2928932", inner_mode); > @@ -322,7 +332,7 @@ run_broadcast_selftests (void) > #define BROADCAST_TEST(MODE_CLASS) > \ > FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT) > \ > { > \ > - if (riscv_v_ext_vector_mode_p (mode)) > \ > + if (riscv_v_ext_vector_mode_p (mode) && !vls_mode_p(mode)) > \ > { > \ > rtx_insn *insn; > \ > rtx src; > \ > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index 99c414cc9102..9d41da945290 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -742,4 +742,16 @@ gen_avl_for_scalar_move (rtx avl) > } > } > > +machine_mode > +minimal_vls_mode (machine_mode) > +{ > + return VNx4SImode; > +} > + > +machine_mode > +mask_mode(machine_mode) > +{ > + return VNx4BImode; > +} > + > } // namespace riscv_vector > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index a2d2dd0bb670..c2bebc42bff7 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -985,6 +985,8 @@ riscv_v_ext_vector_mode_p (machine_mode mode) > switch (mode) > { > #include "riscv-vector-switch.def" > + case E_V4SImode: > + return true; > default: > return false; > } > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index dd845cc1ed33..05b41559ff8e 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -3148,3 +3148,4 @@ > (include "sifive-7.md") > (include "thead.md") > (include "vector.md") > +(include "vector-vls.md") > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index 07bf8bdebffb..cc4a93a87638 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -3535,6 +3535,15 @@ An address that is held in a general-purpose register. > @item S > A constraint that matches an absolute symbolic address. > > +@item vr > +A vector register (if available).. > + > +@item vd > +A vector register, excluding v0 (if available). > + > +@item vm > +A vector register, only v0 (if available). > + > @end table > > @item RX---@file{config/rx/constraints.md} > -- > 2.39.2 >