> +(define_split > + [(set (match_operand:<VM> 0 "register_operand") > + (if_then_else:<VM> > + (unspec:<VM> > + [(match_operand:<VM> 1 "vector_all_trues_mask_operand") > + (match_operand 6 "vector_length_operand") > + (match_operand 7 "const_int_operand") > + (match_operand 8 "const_int_operand") > + (reg:SI VL_REGNUM) > + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) > + (match_operator:<VM> 3 "comparison_simplify_to_clear_operator" > + [(match_operand:VI 4 "register_operand") > + (match_operand:VI 5 "vector_arith_operand")]) > + (match_operand:<VM> 2 "vector_merge_operand")))] > + "TARGET_VECTOR && reload_completed && operands[4] == operands[5]"
Could you try something like this? that should be more generic: (define_split [(set (match_operand:VB 0 "register_operand") (if_then_else:VB (unspec:VB [(match_operand:VB 1 "vector_all_trues_mask_operand") (match_operand 4 "vector_length_operand") (match_operand 5 "const_int_operand") (match_operand 6 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VB 3 "vector_move_operand") (match_operand:VB 2 "vector_undef_operand")))] "TARGET_VECTOR && reload_completed" [(const_int 0)] { emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX (<MODE>mode), RVV_VUNDEF (<MODE>mode), CONST0_RTX (<MODE>mode), operands[4], operands[5])); DONE; } )