On 4/29/23 11:21, Andrew Waterman wrote:
The relevant statement in the spec is that "the tail elements are always
updated with a tail-agnostic policy". The vmset.m instruction will
cause mask register bits [0, vl-1] to be set to 1; elements [vl,
VLMAX-1] will either be undisturbed or set to 1, i.e., effectively
unspecified.
Makes sense. Just have to stitch together bits from different locations
in the manual.
The net being that I can't think we can define that macro for RISC-V in
the way that Pan wants, the semantics just don't line up correctly.
jeff
