[PATCH][committed] aarch64: PR target/99195 annotate more simple binary ops for vec-concat with zero

[Kyrylo Tkachov via Gcc-patches]

Hi all,

More pattern annotations and tests to eliminate redundant vec-concat with zero 
instructions.
These are for the abd family of instructions and the pairwise floating-point 
max/min and fadd
operations too.

Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        PR target/99195
        * config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>): Rename to...
        (aarch64_<su>abd<mode><vczle><vczbe>): ... This.
        (fabd<mode>3): Rename to...
        (fabd<mode>3<vczle><vczbe>): ... This.
        (aarch64_<optab>p<mode>): Rename to...
        (aarch64_<optab>p<mode><vczle><vczbe>): ... This.
        (aarch64_faddp<mode>): Rename to...
        (aarch64_faddp<mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

        PR target/99195
        * gcc.target/aarch64/simd/pr99195_1.c: Add testing for more binary ops.
        * gcc.target/aarch64/simd/pr99195_2.c: Add testing for more binary ops.

vbin.patch
Description: vbin.patch